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Line 38... |
//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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`define EXPAND_TO_IFDEF `ifdef
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`define EXPAND_TO_ELSE `else
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`define EXPAND_TO_ENDIF `endif
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// Global buffer
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// Global buffer
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// usage:
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// usage:
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// use to enable global buffers for high fan out signal such as clock and reset
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// use to enable global buffers for high fan out signals such as clock and reset
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`ifdef ACTEL
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`ifdef ACTEL
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`timescale 1 ns/100 ps
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`timescale 1 ns/100 ps
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// Version: 8.4 8.4.0.33
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// Version: 8.4 8.4.0.33
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endmodule
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endmodule
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`timescale 1 ns/1 ns
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`timescale 1 ns/1 ns
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module vl_gbuf ( i, o);
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module vl_gbuf ( i, o);
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input i;
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input i;
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output o;
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output o;
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//E2_ifdef SIM_GBUF
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assign o=i;
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//E2_else
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gbuf gbuf_i0 ( .CLK(i), .GL(o));
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gbuf gbuf_i0 ( .CLK(i), .GL(o));
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//E2_endif
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endmodule
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endmodule
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`else
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`else
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`ifdef ALTERA
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`ifdef ALTERA
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altera
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altera
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`else
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`else
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`timescale 1 ns/1 ns
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`timescale 1 ns/100 ps
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module vl_gbuf ( i, o);
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module vl_gbuf ( i, o);
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input i;
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input i;
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output o;
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output o;
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assign o = i;
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assign o = i;
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endmodule
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endmodule
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`endif //ACTEL
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`endif //ACTEL
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// sync reset
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// sync reset
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// input active lo async reset, normally from external reset generetaor and/or switch
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// input active lo async reset, normally from external reset generetaor and/or switch
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// output active high global reset sync with two DFFs
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// output active high global reset sync with two DFFs
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`timescale 1 ns/1 ns
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`timescale 1 ns/100 ps
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module vl_sync_rst ( rst_n_i, rst_o, clk);
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module vl_sync_rst ( rst_n_i, rst_o, clk);
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input rst_n_i, clk;
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input rst_n_i, clk;
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output rst_o;
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output rst_o;
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reg [0:1] tmp;
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reg [0:1] tmp;
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always @ (posedge clk or negedge rst_n_i)
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always @ (posedge clk or negedge rst_n_i)
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vl_gbuf buf_i0( .i(tmp[1]), .o(rst_o));
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vl_gbuf buf_i0( .i(tmp[1]), .o(rst_o));
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endmodule
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endmodule
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// vl_pll
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// vl_pll
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`ifdef ACTEL
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`ifdef ACTEL
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`timescale 1 ns/100 ps
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module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
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module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
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parameter index = 0;
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parameter index = 0;
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parameter number_of_clk = 3;
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parameter number_of_clk = 1;
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parameter clk_i_period_time = 20;
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parameter period_time_0 = 20;
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parameter [0:number_of_clk-1] mult = {32'd1,32'd2,32'd2};
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parameter period_time_1 = 20;
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parameter [0:number_of_clk-1] div = {32'd1,32'd3,32'd3};
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parameter period_time_2 = 20;
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parameter lock_delay = 200;
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parameter lock_delay = 2000;
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input clk_i, rst_n_i;
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input clk_i, rst_n_i;
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output lock;
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output lock;
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output reg [0:number_of_clk-1] clk_o;
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output reg [0:number_of_clk-1] clk_o;
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output [0:number_of_clk-1] rst_o;
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output [0:number_of_clk-1] rst_o;
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//E2_ifdef SIM_PLL
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//E2_ifdef SIM_PLL
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always
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#((period_time_0)/2) clk_o[0] <= (!rst_n_i) ? 0 : ~clk_o[0];
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generate if (number_of_clk > 1)
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always
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#((period_time_1)/2) clk_o[1] <= (!rst_n_i) ? 0 : ~clk_o[1];
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endgenerate
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generate if (number_of_clk > 2)
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always
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#((period_time_2)/2) clk_o[2] <= (!rst_n_i) ? 0 : ~clk_o[2];
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endgenerate
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genvar i;
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genvar i;
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generate for (i=0;i<number_of_clk;i=i+1) begin: clock
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generate for (i=0;i<number_of_clk;i=i+1) begin: clock
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always
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#((clk_i_period_time*div[i]/mult[i])/2) clk_o[i] <= (!rst_n_i) ? 0 : ~clk_o[i];
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vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
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vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
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end
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end
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endgenerate
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endgenerate
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assign #lock_delay lock = rst_n_i;
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assign #lock_delay lock = rst_n_i;
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`ifdef ALTERA
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`ifdef ALTERA
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`else
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`else
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// generic PLL
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// generic PLL
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`timescale 1 ns/100 ps
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module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
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module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
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parameter index = 0;
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parameter index = 0;
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parameter number_of_clk = 3;
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parameter number_of_clk = 1;
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parameter clk_i_period_time = 20;
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parameter period_time_0 = 20;
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parameter clk0_feedthrough = 0;
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parameter period_time_1 = 20;
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parameter mult = 1;
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parameter period_time_2 = 20;
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parameter div = 1;
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parameter [0:number_of_clk-1] post_div = {32'd1,32'd3,32'd3};
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parameter lock_delay = 2000;
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parameter lock_delay = 2000;
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input clk_i, rst_n_i;
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input clk_i, rst_n_i;
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output lock;
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output lock;
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output reg [0:number_of_clk-1] clk_o;
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output reg [0:number_of_clk-1] clk_o;
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output [0:number_of_clk-1] rst_o;
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output [0:number_of_clk-1] rst_o;
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genvar i;
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generate if (clk0_feedthrough==1) begin: clk0_feedthrough
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always #(clk_i_period_time/2+0.200) clk_o[0] <= (!rst_n_i) ? 0 : ~clk_o[0];
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generate for (i=clk0_feedthrough;i<number_of_clk;i=i+1) begin: clock
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always
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always
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#((clk_i_period_time*div/mult*post_div[i])/2) clk_o[i] <= (!rst_n_i) ? 0 : ~clk_o[i];
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#((period_time_0)/2) clk_o[0] <= (!rst_n_i) ? 0 : ~clk_o[0];
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generate if (number_of_clk > 1)
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always
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#((period_time_1)/2) clk_o[1] <= (!rst_n_i) ? 0 : ~clk_o[1];
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endgenerate
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generate if (number_of_clk > 2)
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always
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#((period_time_2)/2) clk_o[2] <= (!rst_n_i) ? 0 : ~clk_o[2];
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endgenerate
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genvar i;
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generate for (i=0;i<number_of_clk;i=i+1) begin: clock
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vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
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vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
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end
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end
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endgenerate
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endgenerate
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assign #lock_delay lock = rst_n_i;
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assign #lock_delay lock = rst_n_i;
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