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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [clk_and_reset.v] - Diff between revs 48 and 139

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Rev 48 Rev 139
Line 378... Line 378...
`define MODULE pll
`define MODULE pll
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
`undef MODULE
`undef MODULE
parameter index = 0;
parameter index = 0;
parameter number_of_clk = 1;
parameter number_of_clk = 1;
parameter period_time_0 = 20000;
parameter period_time = 20000;
parameter period_time_1 = 20000;
parameter clk0_mult_by = 1;
parameter period_time_2 = 20000;
parameter clk0_div_by  = 1;
parameter lock_delay = 2000;
parameter clk1_mult_by = 1;
 
parameter clk1_div_by  = 1;
 
parameter clk2_mult_by = 1;
 
parameter clk3_div_by  = 1;
 
parameter clk3_mult_by = 1;
 
parameter clk3_div_by  = 1;
 
parameter clk4_mult_by = 1;
 
parameter clk4_div_by  = 1;
input clk_i, rst_n_i;
input clk_i, rst_n_i;
output lock;
output lock;
output reg [0:number_of_clk-1] clk_o;
output reg [0:number_of_clk-1] clk_o;
output [0:number_of_clk-1] rst_o;
 
 
initial
 
    clk_o = {number_of_clk{1'b0}};
 
 
always
always
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
    #((period_time*clk0_div_by/clk0_mult_by)/2) clk_o[0] <=  (!rst_n_i) ? 1'b0 : ~clk_o[0];
 
 
generate if (number_of_clk > 1)
generate if (number_of_clk > 1)
always
always
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
    #((period_time*clk1_div_by/clk1_mult_by)/2) clk_o[1] <=  (!rst_n_i) ? 1'b0 : ~clk_o[1];
endgenerate
endgenerate
 
 
generate if (number_of_clk > 2)
generate if (number_of_clk > 2)
always
always
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
    #((period_time*clk2_div_by/clk2_mult_by)/2) clk_o[2] <=  (!rst_n_i) ? 1'b0 : ~clk_o[2];
endgenerate
endgenerate
 
 
genvar i;
generate if (number_of_clk > 3)
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
always
`define MODULE sync_rst
    #((period_time*clk3_div_by/clk3_mult_by)/2) clk_o[3] <=  (!rst_n_i) ? 1'b0 : ~clk_o[3];
     `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
endgenerate
`undef MODULE
 
end
generate if (number_of_clk > 4)
 
always
 
    #((period_time*clk4_div_by/clk4_mult_by)/2) clk_o[4] <=  (!rst_n_i) ? 1'b0 : ~clk_o[4];
endgenerate
endgenerate
 
 
assign #lock_delay lock = rst_n_i;
assign #lock_delay lock = rst_n_i;
 
 
endmodule
endmodule

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