| Line 99... |
Line 99... |
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
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vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
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endmodule
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endmodule
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// vl_pll
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// vl_pll
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`ifdef ACTEL
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`ifdef ACTEL
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///////////////////////////////////////////////////////////////////////////////
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`timescale 1 ps/1 ps
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`timescale 1 ps/1 ps
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module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
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module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
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parameter index = 0;
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parameter index = 0;
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parameter number_of_clk = 1;
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parameter number_of_clk = 1;
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parameter period_time_0 = 20000;
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parameter period_time_0 = 20000;
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| Line 195... |
Line 196... |
vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
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vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
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end
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end
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endgenerate
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endgenerate
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endmodule
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endmodule
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//E2_endif
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//E2_endif
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///////////////////////////////////////////////////////////////////////////////
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`else
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`else
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///////////////////////////////////////////////////////////////////////////////
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`ifdef ALTERA
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`ifdef ALTERA
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`timescale 1 ps/1 ps
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module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
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parameter index = 0;
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parameter number_of_clk = 1;
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parameter period_time_0 = 20000;
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parameter period_time_1 = 20000;
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parameter period_time_2 = 20000;
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parameter period_time_3 = 20000;
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parameter period_time_4 = 20000;
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parameter lock_delay = 2000000;
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input clk_i, rst_n_i;
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output lock;
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output reg [0:number_of_clk-1] clk_o;
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output [0:number_of_clk-1] rst_o;
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//E2_ifdef SIM_PLL
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always
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#((period_time_0)/2) clk_o[0] <= (!rst_n_i) ? 0 : ~clk_o[0];
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generate if (number_of_clk > 1)
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always
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#((period_time_1)/2) clk_o[1] <= (!rst_n_i) ? 0 : ~clk_o[1];
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endgenerate
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generate if (number_of_clk > 2)
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always
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#((period_time_2)/2) clk_o[2] <= (!rst_n_i) ? 0 : ~clk_o[2];
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endgenerate
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always
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#((period_time_3)/2) clk_o[3] <= (!rst_n_i) ? 0 : ~clk_o[3];
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endgenerate
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always
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#((period_time_4)/2) clk_o[4] <= (!rst_n_i) ? 0 : ~clk_o[4];
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endgenerate
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genvar i;
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generate for (i=0;i<number_of_clk;i=i+1) begin: clock
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vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
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end
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endgenerate
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assign #lock_delay lock = rst_n_i;
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endmodule
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//E2_else
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generate if (number_of_clk==1 & index==0) begin
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pll0 pll_i0 (.areset(1'b1), .inclk(clk_i), .locked(lock), .c0(clk_o[0]));
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end
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endgenerate // index==0
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generate if (number_of_clk==1 & index==1) begin
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pll1 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
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end
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endgenerate // index==1
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generate if (number_of_clk==1 & index==2) begin
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pll2 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
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end
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endgenerate // index==2
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generate if (number_of_clk==1 & index==3) begin
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pll3 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
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end
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endgenerate // index==3
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|
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generate if (number_of_clk==2 & index==0) begin
|
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pll0 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
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end
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endgenerate // index==0
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generate if (number_of_clk==2 & index==1) begin
|
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pll1 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
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end
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endgenerate // index==1
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generate if (number_of_clk==2 & index==2) begin
|
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pll2 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
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end
|
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endgenerate // index==2
|
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generate if (number_of_clk==2 & index==3) begin
|
|
pll3 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
|
|
end
|
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endgenerate // index==3
|
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|
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generate if (number_of_clk==3 & index==0) begin
|
|
pll0 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
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end
|
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endgenerate // index==0
|
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generate if (number_of_clk==3 & index==1) begin
|
|
pll1 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
|
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end
|
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endgenerate // index==1
|
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generate if (number_of_clk==3 & index==2) begin
|
|
pll2 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
|
|
end
|
|
endgenerate // index==2
|
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generate if (number_of_clk==3 & index==3) begin
|
|
pll3 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
|
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end
|
|
endgenerate // index==3
|
|
|
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generate if (number_of_clk==4 & index==0) begin
|
|
pll0 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
|
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end
|
|
endgenerate // index==0
|
|
generate if (number_of_clk==4 & index==1) begin
|
|
pll1 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2], .c3(clk_o[3]));
|
|
end
|
|
endgenerate // index==1
|
|
generate if (number_of_clk==4 & index==2) begin
|
|
pll2 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2], .c3(clk_o[3]));
|
|
end
|
|
endgenerate // index==2
|
|
generate if (number_of_clk==4 & index==3) begin
|
|
pll3 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2], .c3(clk_o[3]));
|
|
end
|
|
endgenerate // index==3
|
|
|
|
generate if (number_of_clk==5 & index==0) begin
|
|
pll0 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3], .c4(clk_o[4]));
|
|
end
|
|
endgenerate // index==0
|
|
generate if (number_of_clk==5 & index==1) begin
|
|
pll1 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2], .c3(clk_o[3], .c4(clk_o[4]));
|
|
end
|
|
endgenerate // index==1
|
|
generate if (number_of_clk==5 & index==2) begin
|
|
pll2 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2], .c3(clk_o[3], .c4(clk_o[4]));
|
|
end
|
|
endgenerate // index==2
|
|
generate if (number_of_clk==5 & index==3) begin
|
|
pll3 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2], .c3(clk_o[3], .c4(clk_o[4]));
|
|
end
|
|
endgenerate // index==3
|
|
|
|
genvar i;
|
|
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
|
|
vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
|
|
end
|
|
endgenerate
|
|
endmodule
|
|
//E2_endif
|
|
///////////////////////////////////////////////////////////////////////////////
|
|
|
`else
|
`else
|
|
|
// generic PLL
|
// generic PLL
|
`timescale 1 ps/1 ps
|
`timescale 1 ps/1 ps
|
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
|
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
|
