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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [clk_and_reset.v] - Diff between revs 3 and 4

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//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
`define EXPAND_TO_IFDEF `ifdef
 
`define EXPAND_TO_ELSE `else
 
`define EXPAND_TO_ENDIF `endif
 
// Global buffer
// Global buffer
// usage:
// usage:
// use to enable global buffers for high fan out signal such as clock and reset
// use to enable global buffers for high fan out signals such as clock and reset
 
 
`ifdef ACTEL
`ifdef ACTEL
 
 
`timescale 1 ns/100 ps
`timescale 1 ns/100 ps
// Version: 8.4 8.4.0.33
// Version: 8.4 8.4.0.33
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endmodule
endmodule
`timescale 1 ns/1 ns
`timescale 1 ns/1 ns
module vl_gbuf ( i, o);
module vl_gbuf ( i, o);
input i;
input i;
output o;
output o;
 
//E2_ifdef SIM_GBUF
 
assign o=i;
 
//E2_else
gbuf gbuf_i0 ( .CLK(i), .GL(o));
gbuf gbuf_i0 ( .CLK(i), .GL(o));
 
//E2_endif
endmodule
endmodule
`else
`else
`ifdef ALTERA
`ifdef ALTERA
altera
altera
`else
`else
 
 
`timescale 1 ns/1 ns
`timescale 1 ns/100 ps
module vl_gbuf ( i, o);
module vl_gbuf ( i, o);
input i;
input i;
output o;
output o;
assign o = i;
assign o = i;
endmodule
endmodule
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`endif //ACTEL
`endif //ACTEL
 
 
// sync reset
// sync reset
// input active lo async reset, normally from external reset generetaor and/or switch
// input active lo async reset, normally from external reset generetaor and/or switch
// output active high global reset sync with two DFFs 
// output active high global reset sync with two DFFs 
`timescale 1 ns/1 ns
`timescale 1 ns/100 ps
module vl_sync_rst ( rst_n_i, rst_o, clk);
module vl_sync_rst ( rst_n_i, rst_o, clk);
input rst_n_i, clk;
input rst_n_i, clk;
output rst_o;
output rst_o;
reg [0:1] tmp;
reg [0:1] tmp;
always @ (posedge clk or negedge rst_n_i)
always @ (posedge clk or negedge rst_n_i)
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vl_gbuf buf_i0( .i(tmp[1]), .o(rst_o));
vl_gbuf buf_i0( .i(tmp[1]), .o(rst_o));
endmodule
endmodule
 
 
// vl_pll
// vl_pll
`ifdef ACTEL
`ifdef ACTEL
 
`timescale 1 ns/100 ps
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
parameter index = 0;
parameter index = 0;
parameter number_of_clk = 3;
parameter number_of_clk = 1;
parameter clk_i_period_time = 20;
parameter period_time_0 = 20;
parameter [0:number_of_clk-1] mult = {32'd1,32'd2,32'd2};
parameter period_time_1 = 20;
parameter [0:number_of_clk-1] div  = {32'd1,32'd3,32'd3};
parameter period_time_2 = 20;
parameter lock_delay = 200;
parameter lock_delay = 2000;
input clk_i, rst_n_i;
input clk_i, rst_n_i;
output lock;
output lock;
output reg [0:number_of_clk-1] clk_o;
output reg [0:number_of_clk-1] clk_o;
output [0:number_of_clk-1] rst_o;
output [0:number_of_clk-1] rst_o;
 
 
//E2_ifdef SIM_PLL
//E2_ifdef SIM_PLL
 
 
 
always
 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
 
 
 
generate if (number_of_clk > 1)
 
always
 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
 
endgenerate
 
 
 
generate if (number_of_clk > 2)
 
always
 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
 
endgenerate
 
 
genvar i;
genvar i;
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
always
 
     #((clk_i_period_time*div[i]/mult[i])/2) clk_o[i] <=  (!rst_n_i) ? 0 : ~clk_o[i];
 
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
end
end
endgenerate
endgenerate
 
 
assign #lock_delay lock = rst_n_i;
assign #lock_delay lock = rst_n_i;
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`ifdef ALTERA
`ifdef ALTERA
 
 
`else
`else
 
 
// generic PLL
// generic PLL
 
`timescale 1 ns/100 ps
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
parameter index = 0;
parameter index = 0;
parameter number_of_clk = 3;
parameter number_of_clk = 1;
parameter clk_i_period_time = 20;
parameter period_time_0 = 20;
parameter clk0_feedthrough = 0;
parameter period_time_1 = 20;
parameter mult = 1;
parameter period_time_2 = 20;
parameter div  = 1;
 
parameter [0:number_of_clk-1] post_div  = {32'd1,32'd3,32'd3};
 
parameter lock_delay = 2000;
parameter lock_delay = 2000;
input clk_i, rst_n_i;
input clk_i, rst_n_i;
output lock;
output lock;
output reg [0:number_of_clk-1] clk_o;
output reg [0:number_of_clk-1] clk_o;
output [0:number_of_clk-1] rst_o;
output [0:number_of_clk-1] rst_o;
 
 
genvar i;
 
generate if (clk0_feedthrough==1) begin: clk0_feedthrough
 
        always #(clk_i_period_time/2+0.200) clk_o[0] <= (!rst_n_i) ? 0 : ~clk_o[0];
 
generate for (i=clk0_feedthrough;i<number_of_clk;i=i+1) begin: clock
 
always
always
     #((clk_i_period_time*div/mult*post_div[i])/2) clk_o[i] <=  (!rst_n_i) ? 0 : ~clk_o[i];
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
 
 
 
generate if (number_of_clk > 1)
 
always
 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
 
endgenerate
 
 
 
generate if (number_of_clk > 2)
 
always
 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
 
endgenerate
 
 
 
genvar i;
 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
end
end
endgenerate
endgenerate
 
 
assign #lock_delay lock = rst_n_i;
assign #lock_delay lock = rst_n_i;

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