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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [clk_and_reset.v] - Diff between revs 33 and 40

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Line 43... Line 43...
// Global buffer
// Global buffer
// usage:
// usage:
// use to enable global buffers for high fan out signals such as clock and reset
// use to enable global buffers for high fan out signals such as clock and reset
 
 
`ifdef ACTEL
`ifdef ACTEL
 
`ifdef GBUF
`timescale 1 ns/100 ps
`timescale 1 ns/100 ps
// Version: 8.4 8.4.0.33
// Version: 8.4 8.4.0.33
module gbuf(GL,CLK);
module gbuf(GL,CLK);
output GL;
output GL;
input  CLK;
input  CLK;
Line 58... Line 58...
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
 
 
endmodule
endmodule
`timescale 1 ns/1 ns
`timescale 1 ns/1 ns
module vl_gbuf ( i, o);
`define MODULE gbuf
 
module `BASE`MODULE ( i, o);
 
`undef MODULE
input i;
input i;
output o;
output o;
//E2_ifdef SIM_GBUF
//E2_ifdef SIM_GBUF
assign o=i;
assign o=i;
//E2_else
//E2_else
gbuf gbuf_i0 ( .CLK(i), .GL(o));
gbuf gbuf_i0 ( .CLK(i), .GL(o));
//E2_endif
//E2_endif
endmodule
endmodule
 
`endif
 
 
`else
`else
 
 
`ifdef ALTERA
`ifdef ALTERA
 
`ifdef GBUF
//altera
//altera
module vl_gbuf ( i, o);
`define MODULE gbuf
 
module `BASE`MODULE ( i, o);
 
`undef MODULE
input i;
input i;
output o;
output o;
assign o = i;
assign o = i;
endmodule
endmodule
 
`endif
 
 
`else
`else
 
 
 
`ifdef GBUF
`timescale 1 ns/100 ps
`timescale 1 ns/100 ps
module vl_gbuf ( i, o);
`define MODULE
 
module `BASE`MODULE ( i, o);
 
`undef MODULE
input i;
input i;
output o;
output o;
assign o = i;
assign o = i;
endmodule
endmodule
 
`endif
`endif // ALTERA
`endif // ALTERA
`endif //ACTEL
`endif //ACTEL
 
 
 
`ifdef SYNC_RST
// sync reset
// sync reset
// input active lo async reset, normally from external reset generator and/or switch
// input active lo async reset, normally from external reset generator and/or switch
// output active high global reset sync with two DFFs 
// output active high global reset sync with two DFFs 
`timescale 1 ns/100 ps
`timescale 1 ns/100 ps
module vl_sync_rst ( rst_n_i, rst_o, clk);
`define MODULE sync_rst
 
module `BASE`MODULE ( rst_n_i, rst_o, clk);
 
`undef MODULE
input rst_n_i, clk;
input rst_n_i, clk;
output rst_o;
output rst_o;
reg [1:0] tmp;
reg [1:0] tmp;
always @ (posedge clk or negedge rst_n_i)
always @ (posedge clk or negedge rst_n_i)
if (!rst_n_i)
if (!rst_n_i)
        tmp <= 2'b11;
        tmp <= 2'b11;
else
else
        tmp <= {1'b0,tmp[1]};
        tmp <= {1'b0,tmp[1]};
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
`define MODULE gbuf
 
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
 
`undef MODULE
endmodule
endmodule
 
`endif
 
 
 
`ifdef PLL
// vl_pll
// vl_pll
`ifdef ACTEL
`ifdef ACTEL
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
`timescale 1 ps/1 ps
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
`define MODULE pll
 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
 
`undef MODULE
parameter index = 0;
parameter index = 0;
parameter number_of_clk = 1;
parameter number_of_clk = 1;
parameter period_time_0 = 20000;
parameter period_time_0 = 20000;
parameter period_time_1 = 20000;
parameter period_time_1 = 20000;
parameter period_time_2 = 20000;
parameter period_time_2 = 20000;
Line 199... Line 219...
end
end
endgenerate // index==0
endgenerate // index==0
 
 
genvar i;
genvar i;
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
`define MODULE sync_rst
 
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
 
`undef MODULE
end
end
endgenerate
endgenerate
endmodule
endmodule
//E2_endif
//E2_endif
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
Line 212... Line 234...
 
 
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`ifdef ALTERA
`ifdef ALTERA
 
 
`timescale 1 ps/1 ps
`timescale 1 ps/1 ps
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
`define MODULE pll
 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
 
`undef MODULE
parameter index = 0;
parameter index = 0;
parameter number_of_clk = 1;
parameter number_of_clk = 1;
parameter period_time_0 = 20000;
parameter period_time_0 = 20000;
parameter period_time_1 = 20000;
parameter period_time_1 = 20000;
parameter period_time_2 = 20000;
parameter period_time_2 = 20000;
Line 337... Line 361...
//E2_endif
//E2_endif
//E2_endif
//E2_endif
 
 
genvar i;
genvar i;
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
`define MODULE sync_rst
 
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
 
`undef MODULE
end
end
endgenerate
endgenerate
endmodule
endmodule
//E2_endif
//E2_endif
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
 
 
`else
`else
 
 
// generic PLL
// generic PLL
`timescale 1 ps/1 ps
`timescale 1 ps/1 ps
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
`define MODULE pll
 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
 
`undef MODULE
parameter index = 0;
parameter index = 0;
parameter number_of_clk = 1;
parameter number_of_clk = 1;
parameter period_time_0 = 20000;
parameter period_time_0 = 20000;
parameter period_time_1 = 20000;
parameter period_time_1 = 20000;
parameter period_time_2 = 20000;
parameter period_time_2 = 20000;
Line 375... Line 403...
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
endgenerate
endgenerate
 
 
genvar i;
genvar i;
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
`define MODULE sync_rst
 
     `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
 
`undef MODULE
end
end
endgenerate
endgenerate
 
 
assign #lock_delay lock = rst_n_i;
assign #lock_delay lock = rst_n_i;
 
 
endmodule
endmodule
 
 
`endif //altera
`endif //altera
`endif //actel
`endif //actel
 
 
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`undef MODULE
 
`endif
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