URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [counters.v] - Diff between revs 3 and 4

Rev 3	Rev 4
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`//// Public License along with this source; if not, download it ////`	`//// Public License along with this source; if not, download it ////`
`//// from http://www.opencores.org/lgpl.shtml ////`	`//// from http://www.opencores.org/lgpl.shtml ////`
`//// ////`	`//// ////`
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`

	`module cnt_shreg_ce ( cke, q, rst, clk);`

	`parameter length = 4;`
	`input cke;`
	`output reg [0:length-1] q;`
	`input rst;`
	`input clk;`

	`always @ (posedge clk or posedge rst)`
	`if (rst)`
	`q <= {1'b1,{length-1{1'b0}}};`
	`else`
	`if (cke)`
	`q <= q >> 1;`

	`endmodule`

	`module cnt_shreg_ce_clear ( cke, clear, q, rst, clk);`

	`parameter length = 4;`
	`input cke;`
	`input clear;`
	`output reg [0:length-1] q;`
	`input rst;`
	`input clk;`

	`always @ (posedge clk or posedge rst)`
	`if (rst)`
	`q <= {1'b1,{length-1{1'b0}}};`
	`else`
	`if (cke)`
	`if (clear)`
	`q <= {1'b1,{length-1{1'b0}}};`
	`else`
	`q <= q >> 1;`

	`endmodule`



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