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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Diff between revs 61 and 62

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Rev 61	Rev 62
Line 95...	Line 95...
`ifndef SPR	`ifndef SPR
`define SPR	`define SPR
`endif	`endif
`endif	`endif

	`ifdef WB_B3_RAM_BE
	`ifndef WB3_ARBITER_TYPE1
	`define WB3_ARBITER_TYPE1
	`endif
	`ifndef RAM_BE
	`define RAM_BE
	`endif
	`endif

`ifdef WB3_ARBITER_TYPE1	`ifdef WB3_ARBITER_TYPE1
`ifndef SPR	`ifndef SPR
`define SPR	`define SPR
`endif	`endif
`ifndef MUX_ANDOR	`ifndef MUX_ANDOR
Line 233...	Line 242...
`ifndef DPRAM_1R1W	`ifndef DPRAM_1R1W
`define DPRAM_1R1W	`define DPRAM_1R1W
`endif	`endif
`endif	`endif

`ifdef WB_B3_RAM_BE
`ifndef WB3_ARBITER_TYPE1
`define WB3_ARBITER_TYPE1
`endif
`ifndef RAM_BE
`define RAM_BE
`endif
`endif
`No newline at end of file`	`No newline at end of file`

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