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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Diff between revs 92 and 94

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Rev 92 Rev 94
Line 61... Line 61...
`define LATCH
`define LATCH
`define SHREG
`define SHREG
`define SHREG_CE
`define SHREG_CE
`define DELAY
`define DELAY
`define DELAY_EMPTYFLAG
`define DELAY_EMPTYFLAG
 
`define PULSE2TOGGLE
 
`define TOGGLE2PULSE
 
`define SYNCHRONIZER
 
`define CDC
 
 
`define WB3AVALON_BRIDGE
`define WB3AVALON_BRIDGE
`define WB3WB3_BRIDGE
`define WB3WB3_BRIDGE
`define WB3_ARBITER_TYPE1
`define WB3_ARBITER_TYPE1
`define WB_ADR_INC
`define WB_ADR_INC
Line 89... Line 93...
`ifndef GBUF
`ifndef GBUF
`define GBUF
`define GBUF
`endif
`endif
`endif
`endif
 
 
 
`ifdef CDC
 
`ifndef PULSE2TOGGLE
 
`define PULSE2TOGGLE
 
`endif
 
`ifndef TOGGLE2PULSE
 
`define TOGGLE2PULSE
 
`endif
 
`ifndef SYNCHRONIZER
 
`define SYNCHRONIZER
 
`endif
 
`endif
 
 
`ifdef WB_B3_DPRAM
`ifdef WB_B3_DPRAM
`ifndef WB_ADR_INC
`ifndef WB_ADR_INC
`define WB_ADR_INC
`define WB_ADR_INC
`endif
`endif
`ifndef DPRAM_BE_2R2W
`ifndef DPRAM_BE_2R2W

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