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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [io.v] - Diff between revs 45 and 136

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Rev 45 Rev 136
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//// You should have received a copy of the GNU Lesser General    ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
`timescale 1ns/1ns
 
`ifdef O_DFF
`ifdef O_DFF
 
`timescale 1ns/1ns
`define MODULE o_dff
`define MODULE o_dff
module `BASE`MODULE (d_i, o_pad, clk, rst);
module `BASE`MODULE (d_i, o_pad, clk, rst);
`undef MODULE
`undef MODULE
parameter width = 1;
parameter width = 1;
parameter reset_value = {width{1'b0}};
parameter reset_value = {width{1'b0}};
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wire [width-1:0] d_i_int `SYN_KEEP;
wire [width-1:0] d_i_int `SYN_KEEP;
reg  [width-1:0] o_pad_int;
reg  [width-1:0] o_pad_int;
assign d_i_int = d_i;
assign d_i_int = d_i;
genvar i;
genvar i;
generate
generate
for (i=0;i<width;i=i+1) begin
for (i=0;i<width;i=i+1) begin : dffs
    always @ (posedge clk or posedge rst)
    always @ (posedge clk or posedge rst)
    if (rst)
    if (rst)
        o_pad_int[i] <= reset_value[i];
        o_pad_int[i] <= reset_value[i];
    else
    else
        o_pad_int[i] <= d_i_int[i];
        o_pad_int[i] <= d_i_int[i];
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end
end
endgenerate
endgenerate
endmodule
endmodule
`endif
`endif
 
 
`timescale 1ns/1ns
 
`ifdef IO_DFF_OE
`ifdef IO_DFF_OE
 
`timescale 1ns/1ns
`define MODULE io_dff_oe
`define MODULE io_dff_oe
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
`undef MODULE
`undef MODULE
parameter width = 1;
parameter width = 1;
input  [width-1:0] d_o;
input  [width-1:0] d_o;
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reg [width-1:0] oe_q;
reg [width-1:0] oe_q;
reg [width-1:0] d_o_q;
reg [width-1:0] d_o_q;
assign oe_d = {width{oe}};
assign oe_d = {width{oe}};
genvar i;
genvar i;
generate
generate
for (i=0;i<width;i=i+1) begin
for (i=0;i<width;i=i+1) begin : dffs
    always @ (posedge clk or posedge rst)
    always @ (posedge clk or posedge rst)
    if (rst)
    if (rst)
        oe_q[i] <= 1'b0;
        oe_q[i] <= 1'b0;
    else
    else
        oe_q[i] <= oe_d[i];
        oe_q[i] <= oe_d[i];
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end
end
endgenerate
endgenerate
endmodule
endmodule
`endif
`endif
 
 
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`ifdef O_DDR
 
`ifdef ALTERA
 
`define MODULE o_ddr
 
module `BASE`MODULE (d_h_i, d_l_i, o_pad, clk, rst);
 
`undef MODULE
 
parameter width = 1;
 
input  [width-1:0] d_h_i, d_l_i;
 
output [width-1:0] o_pad;
 
input clk, rst;
 
genvar i;
 
generate
 
for (i=0;i<width;i=i+1) begin : ddr
 
    ddio_out ddio_out0( .aclr(rst), .datain_h(d_h_i[i]), .datain_l(d_l_i[i]), .outclock(clk), .dataout(o_pad[i]) );
 
end
 
endgenerate
 
endmodule
 
`else
 
`define MODULE o_ddr
 
module `BASE`MODULE (d_h_i, d_l_i, o_pad, clk, rst);
 
`undef MODULE
 
parameter width = 1;
 
input  [width-1:0] d_h_i, d_l_i;
 
output [width-1:0] o_pad;
 
input clk, rst;
 
reg [width-1:0] ff1;
 
reg [width-1:0] ff2;
 
genvar i;
 
generate
 
for (i=0;i<width;i=i+1) begin : ddr
 
    always @ (posedge clk or posedge rst)
 
    if (rst)
 
        ff1[i] <= 1'b0;
 
    else
 
        ff1[i] <= d_h_i[i];
 
    always @ (posedge clk or posedge rst)
 
    if (rst)
 
        ff2[i] <= 1'b0;
 
    else
 
        ff2[i] <= d_l_i[i];
 
    assign o_pad = (clk) ? ff1 : ff2;
 
end
 
endgenerate
 
endmodule
 
`endif
 
`endif
 
 
 
`ifdef O_CLK
 
`define MODULE o_clk
 
module `BASE`MODULE ( clk_o_pad, clk, rst);
 
`undef MODULE
 
input clk, rst;
 
output clk_o_pad;
 
`define MODULE o_ddr
 
`BASE`MODULE o_ddr0( .d_h_i(1'b1), .d_l_i(1'b0), .o_pad(clk_o_pad), .clk(clk), .rst(rst));
 
`undef MODULE
 
endmodule
 
`endif
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