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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [memories.v] - Diff between revs 111 and 118

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Rev 111 Rev 118
Line 212... Line 212...
   parameter mem_size = 1<<addr_width;
   parameter mem_size = 1<<addr_width;
   input [(data_width-1):0]      d_a;
   input [(data_width-1):0]      d_a;
   input [(addr_width-1):0]       adr_a;
   input [(addr_width-1):0]       adr_a;
   input [(addr_width-1):0]       adr_b;
   input [(addr_width-1):0]       adr_b;
   input                         we_a;
   input                         we_a;
   output [(data_width-1):0]      q_b;
   output reg [(data_width-1):0]          q_b;
   input                         clk_a, clk_b;
   input                         clk_a, clk_b;
   reg [(addr_width-1):0]         adr_b_reg;
 
   reg [data_width-1:0] ram [mem_size-1:0] `SYN_NO_RW_CHECK;
   reg [data_width-1:0] ram [mem_size-1:0] `SYN_NO_RW_CHECK;
 
 
    parameter memory_init = 0;
    parameter memory_init = 0;
    parameter memory_file = "vl_ram.vmem";
    parameter memory_file = "vl_ram.vmem";
    parameter debug = 0;
    parameter debug = 0;
Line 245... Line 244...
    endgenerate
    endgenerate
 
 
   always @ (posedge clk_a)
   always @ (posedge clk_a)
   if (we_a)
   if (we_a)
     ram[adr_a] <= d_a;
     ram[adr_a] <= d_a;
 
 
   always @ (posedge clk_b)
   always @ (posedge clk_b)
   adr_b_reg <= adr_b;
      q_b = ram[adr_b];
   assign q_b = ram[adr_b_reg];
 
 
 
endmodule
endmodule
`endif
`endif
 
 
`ifdef DPRAM_2R1W
`ifdef DPRAM_2R1W
Line 268... Line 267...
   input                         we_a;
   input                         we_a;
   output [(data_width-1):0]      q_b;
   output [(data_width-1):0]      q_b;
   output reg [(data_width-1):0] q_a;
   output reg [(data_width-1):0] q_a;
   input                         clk_a, clk_b;
   input                         clk_a, clk_b;
   reg [(data_width-1):0]         q_b;
   reg [(data_width-1):0]         q_b;
   reg [data_width-1:0] ram [mem_szie-1:0] `SYN_NO_RW_CHECK;
   reg [data_width-1:0] ram [mem_size-1:0] `SYN_NO_RW_CHECK;
 
 
    parameter memory_init = 0;
    parameter memory_init = 0;
    parameter memory_file = "vl_ram.vmem";
    parameter memory_file = "vl_ram.vmem";
    parameter debug = 0;
    parameter debug = 0;
 
 

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