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| Rev 111 |
Rev 118 |
| Line 212... |
Line 212... |
parameter mem_size = 1<<addr_width;
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parameter mem_size = 1<<addr_width;
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input [(data_width-1):0] d_a;
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input [(data_width-1):0] d_a;
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input [(addr_width-1):0] adr_a;
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input [(addr_width-1):0] adr_a;
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input [(addr_width-1):0] adr_b;
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input [(addr_width-1):0] adr_b;
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input we_a;
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input we_a;
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output [(data_width-1):0] q_b;
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output reg [(data_width-1):0] q_b;
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input clk_a, clk_b;
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input clk_a, clk_b;
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reg [(addr_width-1):0] adr_b_reg;
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reg [data_width-1:0] ram [mem_size-1:0] `SYN_NO_RW_CHECK;
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reg [data_width-1:0] ram [mem_size-1:0] `SYN_NO_RW_CHECK;
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parameter memory_init = 0;
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parameter memory_init = 0;
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parameter memory_file = "vl_ram.vmem";
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parameter memory_file = "vl_ram.vmem";
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parameter debug = 0;
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parameter debug = 0;
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endgenerate
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endgenerate
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always @ (posedge clk_a)
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always @ (posedge clk_a)
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if (we_a)
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if (we_a)
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ram[adr_a] <= d_a;
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ram[adr_a] <= d_a;
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always @ (posedge clk_b)
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always @ (posedge clk_b)
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adr_b_reg <= adr_b;
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q_b = ram[adr_b];
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assign q_b = ram[adr_b_reg];
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endmodule
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endmodule
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`endif
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`endif
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`ifdef DPRAM_2R1W
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`ifdef DPRAM_2R1W
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input we_a;
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input we_a;
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output [(data_width-1):0] q_b;
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output [(data_width-1):0] q_b;
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output reg [(data_width-1):0] q_a;
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output reg [(data_width-1):0] q_a;
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input clk_a, clk_b;
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input clk_a, clk_b;
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reg [(data_width-1):0] q_b;
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reg [(data_width-1):0] q_b;
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reg [data_width-1:0] ram [mem_szie-1:0] `SYN_NO_RW_CHECK;
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reg [data_width-1:0] ram [mem_size-1:0] `SYN_NO_RW_CHECK;
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parameter memory_init = 0;
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parameter memory_init = 0;
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parameter memory_file = "vl_ram.vmem";
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parameter memory_file = "vl_ram.vmem";
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parameter debug = 0;
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parameter debug = 0;
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