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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [memories.v] - Diff between revs 125 and 128

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Rev 125 Rev 128
Line 585... Line 585...
 
 
generate
generate
if (a_data_width==32 & b_data_width==16) begin : dpram_3216
if (a_data_width==32 & b_data_width==16) begin : dpram_3216
logic [31:0] temp;
logic [31:0] temp;
`define MODULE dpram_be_2r2w
`define MODULE dpram_be_2r2w
`BASE`MODULE # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file))
`BASE`MODULE # (.a_data_width(32), .b_data_width(32), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file))
`undef MODULE
`undef MODULE
dpram6464 (
dpram3232 (
    .d_a(d_a),
    .d_a(d_a),
    .q_a(q_a),
    .q_a(q_a),
    .adr_a(adr_a),
    .adr_a(adr_a),
    .be_a(be_a),
    .be_a(be_a),
    .we_a(we_a),
    .we_a(we_a),
    .clk_a(clk_a),
    .clk_a(clk_a),
    .d_b({d_b,d_b}),
    .d_b({d_b,d_b}),
    .q_b(temp),
    .q_b(temp),
    .adr_b(adr_b),
    .adr_b(adr_b[b_addr_width-1:1]),
    .be_b({be_b,be_b} & {{2{adr_b[0]}},{2{!adr_b[0]}}}),
    .be_b({be_b,be_b} & {{2{adr_b[0]}},{2{!adr_b[0]}}}),
    .we_b(we_b),
    .we_b(we_b),
    .clk_b(clk_b)
    .clk_b(clk_b)
);
);
 
 
Line 615... Line 615...
 
 
generate
generate
if (a_data_width==32 & b_data_width==64) begin : dpram_3264
if (a_data_width==32 & b_data_width==64) begin : dpram_3264
logic [63:0] temp;
logic [63:0] temp;
`define MODULE dpram_be_2r2w
`define MODULE dpram_be_2r2w
`BASE`MODULE # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file))
`BASE`MODULE # (.a_data_width(32), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file))
`undef MODULE
`undef MODULE
dpram6464 (
dpram6464 (
    .d_a({d_a,d_a}),
    .d_a({d_a,d_a}),
    .q_a(temp),
    .q_a(temp),
    .adr_a(adr_a[a_addr_width-1:1]),
    .adr_a(adr_a[a_addr_width-1:1]),

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