OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [memories.v] - Diff between revs 48 and 60

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 48 Rev 60
Line 112... Line 112...
   output reg [(data_width-1):0] q;
   output reg [(data_width-1):0] q;
   input                         clk;
   input                         clk;
 
 
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
 
 
   parameter init = 0;
   parameter memory_init = 0;
   parameter memory_file = "vl_ram.vmem";
   parameter memory_file = "vl_ram.vmem";
   generate if (init) begin : init_mem
   generate if (memory_init) begin : init_mem
   initial
   initial
     begin
     begin
        $readmemh(memory_file, ram);
        $readmemh(memory_file, ram);
     end
     end
   end
   end
   endgenerate
   endgenerate
 
 
 
//E2_ifdef SYSTEMVERILOG
 
// use a multi-dimensional packed array
 
//to model individual bytes within the word
 
 
 
logic [dat_width/8-1:0][7:0] ram[0:1<<(adr_width-2)-1];// # words = 1 << address width
 
always_ff@(posedge clk)
 
begin
 
    if(we) begin // note: we should have a for statement to support any bus width
 
        if(be[3]) ram[adr[adr_size-2:0]][3] <= d[31:24];
 
        if(be[2]) ram[adr[adr_size-2:0]][2] <= d[23:16];
 
        if(be[1]) ram[adr[adr_size-2:0]][1] <= d[15:8];
 
        if(be[0]) ram[adr[adr_size-2:0]][0] <= d[7:0];
 
    end
 
    q <= ram[raddr];
 
end
 
 
 
//E2_else
 
 
   genvar i;
   genvar i;
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
      always @ (posedge clk)
      always @ (posedge clk)
      if (we & be[i])
      if (we & be[i])
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
Line 133... Line 151...
   endgenerate
   endgenerate
 
 
   always @ (posedge clk)
   always @ (posedge clk)
      q <= ram[adr];
      q <= ram[adr];
 
 
 
//E2_endif
 
 
endmodule
endmodule
`endif
`endif
 
 
`ifdef ACTEL
`ifdef ACTEL
        // ACTEL FPGA should not use logic to handle rw collision
        // ACTEL FPGA should not use logic to handle rw collision

powered by: WebSVN 2.1.0

© copyright 1999-2021 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.