//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Versatile library, memories ////
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//// Versatile library, memories ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// memories ////
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//// memories ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// - add more memory types ////
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//// - add more memory types ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Michael Unneback, unneback@opencores.org ////
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//// - Michael Unneback, unneback@opencores.org ////
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//// ORSoC AB ////
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//// ORSoC AB ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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|
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`ifdef ROM_INIT
|
`ifdef ROM_INIT
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/// ROM
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/// ROM
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`define MODULE rom_init
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`define MODULE rom_init
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module `BASE`MODULE ( adr, q, clk);
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module `BASE`MODULE ( adr, q, clk);
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`undef MODULE
|
`undef MODULE
|
|
|
parameter data_width = 32;
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parameter data_width = 32;
|
parameter addr_width = 8;
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parameter addr_width = 8;
|
input [(addr_width-1):0] adr;
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input [(addr_width-1):0] adr;
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output reg [(data_width-1):0] q;
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output reg [(data_width-1):0] q;
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input clk;
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input clk;
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reg [data_width-1:0] rom [(1<<addr_width)-1:0];
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reg [data_width-1:0] rom [(1<<addr_width)-1:0];
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parameter memory_file = "vl_rom.vmem";
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parameter memory_file = "vl_rom.vmem";
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initial
|
initial
|
begin
|
begin
|
$readmemh(memory_file, rom);
|
$readmemh(memory_file, rom);
|
end
|
end
|
|
|
always @ (posedge clk)
|
always @ (posedge clk)
|
q <= rom[adr];
|
q <= rom[adr];
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|
|
endmodule
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endmodule
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`endif
|
`endif
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|
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`ifdef RAM
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`ifdef RAM
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`define MODULE ram
|
`define MODULE ram
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// Single port RAM
|
// Single port RAM
|
module `BASE`MODULE ( d, adr, we, q, clk);
|
module `BASE`MODULE ( d, adr, we, q, clk);
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`undef MODULE
|
`undef MODULE
|
|
|
parameter data_width = 32;
|
parameter data_width = 32;
|
parameter addr_width = 8;
|
parameter addr_width = 8;
|
input [(data_width-1):0] d;
|
input [(data_width-1):0] d;
|
input [(addr_width-1):0] adr;
|
input [(addr_width-1):0] adr;
|
input we;
|
input we;
|
output reg [(data_width-1):0] q;
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output reg [(data_width-1):0] q;
|
input clk;
|
input clk;
|
reg [data_width-1:0] ram [(1<<addr_width)-1:0];
|
reg [data_width-1:0] ram [(1<<addr_width)-1:0];
|
parameter init = 0;
|
parameter init = 0;
|
parameter memory_file = "vl_ram.vmem";
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parameter memory_file = "vl_ram.vmem";
|
generate if (init) begin : init_mem
|
generate if (init) begin : init_mem
|
initial
|
initial
|
begin
|
begin
|
$readmemh(memory_file, ram);
|
$readmemh(memory_file, ram);
|
end
|
end
|
end
|
end
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endgenerate
|
endgenerate
|
|
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin
|
begin
|
if (we)
|
if (we)
|
ram[adr] <= d;
|
ram[adr] <= d;
|
q <= ram[adr];
|
q <= ram[adr];
|
end
|
end
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|
|
endmodule
|
endmodule
|
`endif
|
`endif
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|
|
`ifdef RAM_BE
|
`ifdef RAM_BE
|
`define MODULE ram_be
|
`define MODULE ram_be
|
module `BASE`MODULE ( d, adr, be, we, q, clk);
|
module `BASE`MODULE ( d, adr, be, we, q, clk);
|
`undef MODULE
|
`undef MODULE
|
|
|
parameter data_width = 32;
|
parameter data_width = 32;
|
parameter addr_width = 8;
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parameter addr_width = 8;
|
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parameter mem_size = 256;
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input [(data_width-1):0] d;
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input [(data_width-1):0] d;
|
input [(addr_width-1):0] adr;
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input [(addr_width-1):0] adr;
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input [(addr_width/4)-1:0] be;
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input [(addr_width/4)-1:0] be;
|
input we;
|
input we;
|
output reg [(data_width-1):0] q;
|
output reg [(data_width-1):0] q;
|
input clk;
|
input clk;
|
|
|
//E2_ifdef SYSTEMVERILOG
|
//E2_ifdef SYSTEMVERILOG
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logic [data_width/8-1:0][7:0] ram[0:1<<(addr_width-2)-1];// # words = 1 << address width
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logic [data_width/8-1:0][7:0] ram[0:mem_size-1];// # words = 1 << address width
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//E2_else
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//E2_else
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reg [data_width-1:0] ram [(1<<addr_width)-1:0];
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reg [data_width-1:0] ram [mem_size-1:0];
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//E2_endif
|
//E2_endif
|
|
|
parameter memory_init = 0;
|
parameter memory_init = 0;
|
parameter memory_file = "vl_ram.vmem";
|
parameter memory_file = "vl_ram.vmem";
|
generate if (memory_init) begin : init_mem
|
generate if (memory_init) begin : init_mem
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initial
|
initial
|
begin
|
begin
|
$readmemh(memory_file, ram);
|
$readmemh(memory_file, ram);
|
end
|
end
|
end
|
end
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endgenerate
|
endgenerate
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|
|
//E2_ifdef SYSTEMVERILOG
|
//E2_ifdef SYSTEMVERILOG
|
// use a multi-dimensional packed array
|
// use a multi-dimensional packed array
|
//to model individual bytes within the word
|
//to model individual bytes within the word
|
|
|
always_ff@(posedge clk)
|
always_ff@(posedge clk)
|
begin
|
begin
|
if(we) begin // note: we should have a for statement to support any bus width
|
if(we) begin // note: we should have a for statement to support any bus width
|
if(be[3]) ram[adr[addr_width-2:0]][3] <= d[31:24];
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if(be[3]) ram[adr[addr_width-2:0]][3] <= d[31:24];
|
if(be[2]) ram[adr[addr_width-2:0]][2] <= d[23:16];
|
if(be[2]) ram[adr[addr_width-2:0]][2] <= d[23:16];
|
if(be[1]) ram[adr[addr_width-2:0]][1] <= d[15:8];
|
if(be[1]) ram[adr[addr_width-2:0]][1] <= d[15:8];
|
if(be[0]) ram[adr[addr_width-2:0]][0] <= d[7:0];
|
if(be[0]) ram[adr[addr_width-2:0]][0] <= d[7:0];
|
end
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end
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q <= ram[adr];
|
q <= ram[adr];
|
end
|
end
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|
|
//E2_else
|
//E2_else
|
|
|
genvar i;
|
genvar i;
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generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
|
generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
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always @ (posedge clk)
|
always @ (posedge clk)
|
if (we & be[i])
|
if (we & be[i])
|
ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
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ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
|
end
|
end
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endgenerate
|
endgenerate
|
|
|
always @ (posedge clk)
|
always @ (posedge clk)
|
q <= ram[adr];
|
q <= ram[adr];
|
|
|
//E2_endif
|
//E2_endif
|
|
|
endmodule
|
endmodule
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`endif
|
`endif
|
|
|
`ifdef ACTEL
|
`ifdef ACTEL
|
// ACTEL FPGA should not use logic to handle rw collision
|
// ACTEL FPGA should not use logic to handle rw collision
|
`define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
|
`define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
|
`else
|
`else
|
`define SYN
|
`define SYN
|
`endif
|
`endif
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|
|
`ifdef DPRAM_1R1W
|
`ifdef DPRAM_1R1W
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`define MODULE dpram_1r1w
|
`define MODULE dpram_1r1w
|
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
|
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
|
`undef MODULE
|
`undef MODULE
|
parameter data_width = 32;
|
parameter data_width = 32;
|
parameter addr_width = 8;
|
parameter addr_width = 8;
|
input [(data_width-1):0] d_a;
|
input [(data_width-1):0] d_a;
|
input [(addr_width-1):0] adr_a;
|
input [(addr_width-1):0] adr_a;
|
input [(addr_width-1):0] adr_b;
|
input [(addr_width-1):0] adr_b;
|
input we_a;
|
input we_a;
|
output [(data_width-1):0] q_b;
|
output [(data_width-1):0] q_b;
|
input clk_a, clk_b;
|
input clk_a, clk_b;
|
reg [(addr_width-1):0] adr_b_reg;
|
reg [(addr_width-1):0] adr_b_reg;
|
reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
|
reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
|
|
|
parameter init = 0;
|
parameter init = 0;
|
parameter memory_file = "vl_ram.vmem";
|
parameter memory_file = "vl_ram.vmem";
|
generate if (init) begin : init_mem
|
generate if (init) begin : init_mem
|
initial
|
initial
|
begin
|
begin
|
$readmemh(memory_file, ram);
|
$readmemh(memory_file, ram);
|
end
|
end
|
end
|
end
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endgenerate
|
endgenerate
|
|
|
always @ (posedge clk_a)
|
always @ (posedge clk_a)
|
if (we_a)
|
if (we_a)
|
ram[adr_a] <= d_a;
|
ram[adr_a] <= d_a;
|
always @ (posedge clk_b)
|
always @ (posedge clk_b)
|
adr_b_reg <= adr_b;
|
adr_b_reg <= adr_b;
|
assign q_b = ram[adr_b_reg];
|
assign q_b = ram[adr_b_reg];
|
|
|
endmodule
|
endmodule
|
`endif
|
`endif
|
|
|
`ifdef DPRAM_2R1W
|
`ifdef DPRAM_2R1W
|
`define MODULE dpram_2r1w
|
`define MODULE dpram_2r1w
|
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
|
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
|
`undef MODULE
|
`undef MODULE
|
|
|
parameter data_width = 32;
|
parameter data_width = 32;
|
parameter addr_width = 8;
|
parameter addr_width = 8;
|
input [(data_width-1):0] d_a;
|
input [(data_width-1):0] d_a;
|
input [(addr_width-1):0] adr_a;
|
input [(addr_width-1):0] adr_a;
|
input [(addr_width-1):0] adr_b;
|
input [(addr_width-1):0] adr_b;
|
input we_a;
|
input we_a;
|
output [(data_width-1):0] q_b;
|
output [(data_width-1):0] q_b;
|
output reg [(data_width-1):0] q_a;
|
output reg [(data_width-1):0] q_a;
|
input clk_a, clk_b;
|
input clk_a, clk_b;
|
reg [(data_width-1):0] q_b;
|
reg [(data_width-1):0] q_b;
|
reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
|
reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
|
|
|
parameter init = 0;
|
parameter init = 0;
|
parameter memory_file = "vl_ram.vmem";
|
parameter memory_file = "vl_ram.vmem";
|
generate if (init) begin : init_mem
|
generate if (init) begin : init_mem
|
initial
|
initial
|
begin
|
begin
|
$readmemh(memory_file, ram);
|
$readmemh(memory_file, ram);
|
end
|
end
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
always @ (posedge clk_a)
|
always @ (posedge clk_a)
|
begin
|
begin
|
q_a <= ram[adr_a];
|
q_a <= ram[adr_a];
|
if (we_a)
|
if (we_a)
|
ram[adr_a] <= d_a;
|
ram[adr_a] <= d_a;
|
end
|
end
|
always @ (posedge clk_b)
|
always @ (posedge clk_b)
|
q_b <= ram[adr_b];
|
q_b <= ram[adr_b];
|
endmodule
|
endmodule
|
`endif
|
`endif
|
|
|
`ifdef DPRAM_2R2W
|
`ifdef DPRAM_2R2W
|
`define MODULE dpram_2r2w
|
`define MODULE dpram_2r2w
|
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
|
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
|
`undef MODULE
|
`undef MODULE
|
|
|
parameter data_width = 32;
|
parameter data_width = 32;
|
parameter addr_width = 8;
|
parameter addr_width = 8;
|
input [(data_width-1):0] d_a;
|
input [(data_width-1):0] d_a;
|
input [(addr_width-1):0] adr_a;
|
input [(addr_width-1):0] adr_a;
|
input [(addr_width-1):0] adr_b;
|
input [(addr_width-1):0] adr_b;
|
input we_a;
|
input we_a;
|
output [(data_width-1):0] q_b;
|
output [(data_width-1):0] q_b;
|
input [(data_width-1):0] d_b;
|
input [(data_width-1):0] d_b;
|
output reg [(data_width-1):0] q_a;
|
output reg [(data_width-1):0] q_a;
|
input we_b;
|
input we_b;
|
input clk_a, clk_b;
|
input clk_a, clk_b;
|
reg [(data_width-1):0] q_b;
|
reg [(data_width-1):0] q_b;
|
reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
|
reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
|
|
|
parameter init = 0;
|
parameter init = 0;
|
parameter memory_file = "vl_ram.vmem";
|
parameter memory_file = "vl_ram.vmem";
|
generate if (init) begin : init_mem
|
generate if (init) begin : init_mem
|
initial
|
initial
|
begin
|
begin
|
$readmemh(memory_file, ram);
|
$readmemh(memory_file, ram);
|
end
|
end
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
always @ (posedge clk_a)
|
always @ (posedge clk_a)
|
begin
|
begin
|
q_a <= ram[adr_a];
|
q_a <= ram[adr_a];
|
if (we_a)
|
if (we_a)
|
ram[adr_a] <= d_a;
|
ram[adr_a] <= d_a;
|
end
|
end
|
always @ (posedge clk_b)
|
always @ (posedge clk_b)
|
begin
|
begin
|
q_b <= ram[adr_b];
|
q_b <= ram[adr_b];
|
if (we_b)
|
if (we_b)
|
ram[adr_b] <= d_b;
|
ram[adr_b] <= d_b;
|
end
|
end
|
endmodule
|
endmodule
|
`endif
|
`endif
|
|
|
// Content addresable memory, CAM
|
// Content addresable memory, CAM
|
|
|
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
|
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
|
// FIFO
|
// FIFO
|
`define MODULE fifo_1r1w_fill_level_sync
|
`define MODULE fifo_1r1w_fill_level_sync
|
module `BASE`MODULE (
|
module `BASE`MODULE (
|
`undef MODULE
|
`undef MODULE
|
d, wr, fifo_full,
|
d, wr, fifo_full,
|
q, rd, fifo_empty,
|
q, rd, fifo_empty,
|
fill_level,
|
fill_level,
|
clk, rst
|
clk, rst
|
);
|
);
|
|
|
parameter data_width = 18;
|
parameter data_width = 18;
|
parameter addr_width = 4;
|
parameter addr_width = 4;
|
|
|
// write side
|
// write side
|
input [data_width-1:0] d;
|
input [data_width-1:0] d;
|
input wr;
|
input wr;
|
output fifo_full;
|
output fifo_full;
|
// read side
|
// read side
|
output [data_width-1:0] q;
|
output [data_width-1:0] q;
|
input rd;
|
input rd;
|
output fifo_empty;
|
output fifo_empty;
|
// common
|
// common
|
output [addr_width:0] fill_level;
|
output [addr_width:0] fill_level;
|
input rst, clk;
|
input rst, clk;
|
|
|
wire [addr_width:1] wadr, radr;
|
wire [addr_width:1] wadr, radr;
|
|
|
`define MODULE cnt_bin_ce
|
`define MODULE cnt_bin_ce
|
`BASE`MODULE
|
`BASE`MODULE
|
# ( .length(addr_width))
|
# ( .length(addr_width))
|
fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
|
fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
|
`BASE`MODULE
|
`BASE`MODULE
|
# (.length(addr_width))
|
# (.length(addr_width))
|
fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
|
fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
|
`undef MODULE
|
`undef MODULE
|
|
|
`define MODULE dpram_1r1w
|
`define MODULE dpram_1r1w
|
`BASE`MODULE
|
`BASE`MODULE
|
# (.data_width(data_width), .addr_width(addr_width))
|
# (.data_width(data_width), .addr_width(addr_width))
|
dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
|
dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
|
`undef MODULE
|
`undef MODULE
|
|
|
`define MODULE cnt_bin_ce_rew_q_zq_l1
|
`define MODULE cnt_bin_ce_rew_q_zq_l1
|
`BASE`MODULE
|
`BASE`MODULE
|
# (.length(addr_width+1), .level1_value(1<<addr_width))
|
# (.length(addr_width+1), .level1_value(1<<addr_width))
|
fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
|
fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
|
`undef MODULE
|
`undef MODULE
|
endmodule
|
endmodule
|
`endif
|
`endif
|
|
|
`ifdef FIFO_2R2W_SYNC_SIMPLEX
|
`ifdef FIFO_2R2W_SYNC_SIMPLEX
|
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
|
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
|
// RAM is supposed to be larger than the two FIFOs
|
// RAM is supposed to be larger than the two FIFOs
|
// LFSR counters used adr pointers
|
// LFSR counters used adr pointers
|
`define MODULE fifo_2r2w_sync_simplex
|
`define MODULE fifo_2r2w_sync_simplex
|
module `BASE`MODULE (
|
module `BASE`MODULE (
|
`undef MODULE
|
`undef MODULE
|
// a side
|
// a side
|
a_d, a_wr, a_fifo_full,
|
a_d, a_wr, a_fifo_full,
|
a_q, a_rd, a_fifo_empty,
|
a_q, a_rd, a_fifo_empty,
|
a_fill_level,
|
a_fill_level,
|
// b side
|
// b side
|
b_d, b_wr, b_fifo_full,
|
b_d, b_wr, b_fifo_full,
|
b_q, b_rd, b_fifo_empty,
|
b_q, b_rd, b_fifo_empty,
|
b_fill_level,
|
b_fill_level,
|
// common
|
// common
|
clk, rst
|
clk, rst
|
);
|
);
|
parameter data_width = 8;
|
parameter data_width = 8;
|
parameter addr_width = 5;
|
parameter addr_width = 5;
|
parameter fifo_full_level = (1<<addr_width)-1;
|
parameter fifo_full_level = (1<<addr_width)-1;
|
|
|
// a side
|
// a side
|
input [data_width-1:0] a_d;
|
input [data_width-1:0] a_d;
|
input a_wr;
|
input a_wr;
|
output a_fifo_full;
|
output a_fifo_full;
|
output [data_width-1:0] a_q;
|
output [data_width-1:0] a_q;
|
input a_rd;
|
input a_rd;
|
output a_fifo_empty;
|
output a_fifo_empty;
|
output [addr_width-1:0] a_fill_level;
|
output [addr_width-1:0] a_fill_level;
|
|
|
// b side
|
// b side
|
input [data_width-1:0] b_d;
|
input [data_width-1:0] b_d;
|
input b_wr;
|
input b_wr;
|
output b_fifo_full;
|
output b_fifo_full;
|
output [data_width-1:0] b_q;
|
output [data_width-1:0] b_q;
|
input b_rd;
|
input b_rd;
|
output b_fifo_empty;
|
output b_fifo_empty;
|
output [addr_width-1:0] b_fill_level;
|
output [addr_width-1:0] b_fill_level;
|
|
|
input clk;
|
input clk;
|
input rst;
|
input rst;
|
|
|
// adr_gen
|
// adr_gen
|
wire [addr_width:1] a_wadr, a_radr;
|
wire [addr_width:1] a_wadr, a_radr;
|
wire [addr_width:1] b_wadr, b_radr;
|
wire [addr_width:1] b_wadr, b_radr;
|
// dpram
|
// dpram
|
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
|
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
|
|
|
`define MODULE cnt_lfsr_ce
|
`define MODULE cnt_lfsr_ce
|
`BASE`MODULE
|
`BASE`MODULE
|
# ( .length(addr_width))
|
# ( .length(addr_width))
|
fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
|
fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
|
|
|
`BASE`MODULE
|
`BASE`MODULE
|
# (.length(addr_width))
|
# (.length(addr_width))
|
fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
|
fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
|
|
|
`BASE`MODULE
|
`BASE`MODULE
|
# ( .length(addr_width))
|
# ( .length(addr_width))
|
fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
|
fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
|
|
|
`BASE`MODULE
|
`BASE`MODULE
|
# (.length(addr_width))
|
# (.length(addr_width))
|
fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
|
fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
|
`undef MODULE
|
`undef MODULE
|
|
|
// mux read or write adr to DPRAM
|
// mux read or write adr to DPRAM
|
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
|
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
|
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
|
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
|
|
|
`define MODULE dpram_2r2w
|
`define MODULE dpram_2r2w
|
`BASE`MODULE
|
`BASE`MODULE
|
# (.data_width(data_width), .addr_width(addr_width+1))
|
# (.data_width(data_width), .addr_width(addr_width+1))
|
dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
|
dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
|
.d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
|
.d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
|
`undef MODULE
|
`undef MODULE
|
|
|
`define MODULE cnt_bin_ce_rew_zq_l1
|
`define MODULE cnt_bin_ce_rew_zq_l1
|
`BASE`MODULE
|
`BASE`MODULE
|
# (.length(addr_width), .level1_value(fifo_full_level))
|
# (.length(addr_width), .level1_value(fifo_full_level))
|
a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
|
a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
|
|
|
`BASE`MODULE
|
`BASE`MODULE
|
# (.length(addr_width), .level1_value(fifo_full_level))
|
# (.length(addr_width), .level1_value(fifo_full_level))
|
b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
|
b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
|
`undef MODULE
|
`undef MODULE
|
|
|
endmodule
|
endmodule
|
`endif
|
`endif
|
|
|
`ifdef FIFO_CMP_ASYNC
|
`ifdef FIFO_CMP_ASYNC
|
`define MODULE fifo_cmp_async
|
`define MODULE fifo_cmp_async
|
module `BASE`MODULE ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
|
module `BASE`MODULE ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
|
`undef MODULE
|
`undef MODULE
|
|
|
parameter addr_width = 4;
|
parameter addr_width = 4;
|
parameter N = addr_width-1;
|
parameter N = addr_width-1;
|
|
|
parameter Q1 = 2'b00;
|
parameter Q1 = 2'b00;
|
parameter Q2 = 2'b01;
|
parameter Q2 = 2'b01;
|
parameter Q3 = 2'b11;
|
parameter Q3 = 2'b11;
|
parameter Q4 = 2'b10;
|
parameter Q4 = 2'b10;
|
|
|
parameter going_empty = 1'b0;
|
parameter going_empty = 1'b0;
|
parameter going_full = 1'b1;
|
parameter going_full = 1'b1;
|
|
|
input [N:0] wptr, rptr;
|
input [N:0] wptr, rptr;
|
output fifo_empty;
|
output fifo_empty;
|
output fifo_full;
|
output fifo_full;
|
input wclk, rclk, rst;
|
input wclk, rclk, rst;
|
|
|
`ifndef GENERATE_DIRECTION_AS_LATCH
|
`ifndef GENERATE_DIRECTION_AS_LATCH
|
wire direction;
|
wire direction;
|
`endif
|
`endif
|
`ifdef GENERATE_DIRECTION_AS_LATCH
|
`ifdef GENERATE_DIRECTION_AS_LATCH
|
reg direction;
|
reg direction;
|
`endif
|
`endif
|
reg direction_set, direction_clr;
|
reg direction_set, direction_clr;
|
|
|
wire async_empty, async_full;
|
wire async_empty, async_full;
|
wire fifo_full2;
|
wire fifo_full2;
|
wire fifo_empty2;
|
wire fifo_empty2;
|
|
|
// direction_set
|
// direction_set
|
always @ (wptr[N:N-1] or rptr[N:N-1])
|
always @ (wptr[N:N-1] or rptr[N:N-1])
|
case ({wptr[N:N-1],rptr[N:N-1]})
|
case ({wptr[N:N-1],rptr[N:N-1]})
|
{Q1,Q2} : direction_set <= 1'b1;
|
{Q1,Q2} : direction_set <= 1'b1;
|
{Q2,Q3} : direction_set <= 1'b1;
|
{Q2,Q3} : direction_set <= 1'b1;
|
{Q3,Q4} : direction_set <= 1'b1;
|
{Q3,Q4} : direction_set <= 1'b1;
|
{Q4,Q1} : direction_set <= 1'b1;
|
{Q4,Q1} : direction_set <= 1'b1;
|
default : direction_set <= 1'b0;
|
default : direction_set <= 1'b0;
|
endcase
|
endcase
|
|
|
// direction_clear
|
// direction_clear
|
always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
|
always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
|
if (rst)
|
if (rst)
|
direction_clr <= 1'b1;
|
direction_clr <= 1'b1;
|
else
|
else
|
case ({wptr[N:N-1],rptr[N:N-1]})
|
case ({wptr[N:N-1],rptr[N:N-1]})
|
{Q2,Q1} : direction_clr <= 1'b1;
|
{Q2,Q1} : direction_clr <= 1'b1;
|
{Q3,Q2} : direction_clr <= 1'b1;
|
{Q3,Q2} : direction_clr <= 1'b1;
|
{Q4,Q3} : direction_clr <= 1'b1;
|
{Q4,Q3} : direction_clr <= 1'b1;
|
{Q1,Q4} : direction_clr <= 1'b1;
|
{Q1,Q4} : direction_clr <= 1'b1;
|
default : direction_clr <= 1'b0;
|
default : direction_clr <= 1'b0;
|
endcase
|
endcase
|
|
|
`define MODULE dff_sr
|
`define MODULE dff_sr
|
`ifndef GENERATE_DIRECTION_AS_LATCH
|
`ifndef GENERATE_DIRECTION_AS_LATCH
|
`BASE`MODULE dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
|
`BASE`MODULE dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
|
`endif
|
`endif
|
|
|
`ifdef GENERATE_DIRECTION_AS_LATCH
|
`ifdef GENERATE_DIRECTION_AS_LATCH
|
always @ (posedge direction_set or posedge direction_clr)
|
always @ (posedge direction_set or posedge direction_clr)
|
if (direction_clr)
|
if (direction_clr)
|
direction <= going_empty;
|
direction <= going_empty;
|
else
|
else
|
direction <= going_full;
|
direction <= going_full;
|
`endif
|
`endif
|
|
|
assign async_empty = (wptr == rptr) && (direction==going_empty);
|
assign async_empty = (wptr == rptr) && (direction==going_empty);
|
assign async_full = (wptr == rptr) && (direction==going_full);
|
assign async_full = (wptr == rptr) && (direction==going_full);
|
|
|
`BASE`MODULE dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
|
`BASE`MODULE dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
|
`BASE`MODULE dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
|
`BASE`MODULE dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
|
`undef MODULE
|
`undef MODULE
|
|
|
/*
|
/*
|
always @ (posedge wclk or posedge rst or posedge async_full)
|
always @ (posedge wclk or posedge rst or posedge async_full)
|
if (rst)
|
if (rst)
|
{fifo_full, fifo_full2} <= 2'b00;
|
{fifo_full, fifo_full2} <= 2'b00;
|
else if (async_full)
|
else if (async_full)
|
{fifo_full, fifo_full2} <= 2'b11;
|
{fifo_full, fifo_full2} <= 2'b11;
|
else
|
else
|
{fifo_full, fifo_full2} <= {fifo_full2, async_full};
|
{fifo_full, fifo_full2} <= {fifo_full2, async_full};
|
*/
|
*/
|
/* always @ (posedge rclk or posedge async_empty)
|
/* always @ (posedge rclk or posedge async_empty)
|
if (async_empty)
|
if (async_empty)
|
{fifo_empty, fifo_empty2} <= 2'b11;
|
{fifo_empty, fifo_empty2} <= 2'b11;
|
else
|
else
|
{fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
|
{fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
|
`define MODULE dff
|
`define MODULE dff
|
`BASE`MODULE # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
|
`BASE`MODULE # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
|
`BASE`MODULE # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty), .clk(rclk), .rst(async_empty));
|
`BASE`MODULE # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty), .clk(rclk), .rst(async_empty));
|
`undef MODULE
|
`undef MODULE
|
endmodule // async_compb
|
endmodule // async_compb
|
`endif
|
`endif
|
|
|
`ifdef FIFO_1R1W_ASYNC
|
`ifdef FIFO_1R1W_ASYNC
|
`define MODULE fifo_1r1w_async
|
`define MODULE fifo_1r1w_async
|
module `BASE`MODULE (
|
module `BASE`MODULE (
|
`undef MODULE
|
`undef MODULE
|
d, wr, fifo_full, wr_clk, wr_rst,
|
d, wr, fifo_full, wr_clk, wr_rst,
|
q, rd, fifo_empty, rd_clk, rd_rst
|
q, rd, fifo_empty, rd_clk, rd_rst
|
);
|
);
|
|
|
parameter data_width = 18;
|
parameter data_width = 18;
|
parameter addr_width = 4;
|
parameter addr_width = 4;
|
|
|
// write side
|
// write side
|
input [data_width-1:0] d;
|
input [data_width-1:0] d;
|
input wr;
|
input wr;
|
output fifo_full;
|
output fifo_full;
|
input wr_clk;
|
input wr_clk;
|
input wr_rst;
|
input wr_rst;
|
// read side
|
// read side
|
output [data_width-1:0] q;
|
output [data_width-1:0] q;
|
input rd;
|
input rd;
|
output fifo_empty;
|
output fifo_empty;
|
input rd_clk;
|
input rd_clk;
|
input rd_rst;
|
input rd_rst;
|
|
|
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
|
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
|
|
|
`define MODULE cnt_gray_ce_bin
|
`define MODULE cnt_gray_ce_bin
|
`BASE`MODULE
|
`BASE`MODULE
|
# ( .length(addr_width))
|
# ( .length(addr_width))
|
fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
|
fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
|
|
|
`BASE`MODULE
|
`BASE`MODULE
|
# (.length(addr_width))
|
# (.length(addr_width))
|
fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
|
fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
|
`undef MODULE
|
`undef MODULE
|
|
|
`define MODULE dpram_1r1w
|
`define MODULE dpram_1r1w
|
`BASE`MODULE
|
`BASE`MODULE
|
# (.data_width(data_width), .addr_width(addr_width))
|
# (.data_width(data_width), .addr_width(addr_width))
|
dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
|
dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
|
`undef MODULE
|
`undef MODULE
|
|
|
`define MODULE fifo_cmp_async
|
`define MODULE fifo_cmp_async
|
`BASE`MODULE
|
`BASE`MODULE
|
# (.addr_width(addr_width))
|
# (.addr_width(addr_width))
|
cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
|
cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
|
`undef MODULE
|
`undef MODULE
|
|
|
endmodule
|
endmodule
|
`endif
|
`endif
|
|
|
`ifdef FIFO_2R2W_ASYNC
|
`ifdef FIFO_2R2W_ASYNC
|
`define MODULE fifo_2r2w_async
|
`define MODULE fifo_2r2w_async
|
module `BASE`MODULE (
|
module `BASE`MODULE (
|
`undef MODULE
|
`undef MODULE
|
// a side
|
// a side
|
a_d, a_wr, a_fifo_full,
|
a_d, a_wr, a_fifo_full,
|
a_q, a_rd, a_fifo_empty,
|
a_q, a_rd, a_fifo_empty,
|
a_clk, a_rst,
|
a_clk, a_rst,
|
// b side
|
// b side
|
b_d, b_wr, b_fifo_full,
|
b_d, b_wr, b_fifo_full,
|
b_q, b_rd, b_fifo_empty,
|
b_q, b_rd, b_fifo_empty,
|
b_clk, b_rst
|
b_clk, b_rst
|
);
|
);
|
|
|
parameter data_width = 18;
|
parameter data_width = 18;
|
parameter addr_width = 4;
|
parameter addr_width = 4;
|
|
|
// a side
|
// a side
|
input [data_width-1:0] a_d;
|
input [data_width-1:0] a_d;
|
input a_wr;
|
input a_wr;
|
output a_fifo_full;
|
output a_fifo_full;
|
output [data_width-1:0] a_q;
|
output [data_width-1:0] a_q;
|
input a_rd;
|
input a_rd;
|
output a_fifo_empty;
|
output a_fifo_empty;
|
input a_clk;
|
input a_clk;
|
input a_rst;
|
input a_rst;
|
|
|
// b side
|
// b side
|
input [data_width-1:0] b_d;
|
input [data_width-1:0] b_d;
|
input b_wr;
|
input b_wr;
|
output b_fifo_full;
|
output b_fifo_full;
|
output [data_width-1:0] b_q;
|
output [data_width-1:0] b_q;
|
input b_rd;
|
input b_rd;
|
output b_fifo_empty;
|
output b_fifo_empty;
|
input b_clk;
|
input b_clk;
|
input b_rst;
|
input b_rst;
|
|
|
`define MODULE fifo_1r1w_async
|
`define MODULE fifo_1r1w_async
|
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
|
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
|
vl_fifo_1r1w_async_a (
|
vl_fifo_1r1w_async_a (
|
.d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
|
.d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
|
.q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
|
.q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
|
);
|
);
|
|
|
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
|
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
|
vl_fifo_1r1w_async_b (
|
vl_fifo_1r1w_async_b (
|
.d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
|
.d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
|
.q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
|
.q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
|
);
|
);
|
`undef MODULE
|
`undef MODULE
|
|
|
endmodule
|
endmodule
|
`endif
|
`endif
|
|
|
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
|
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
|
`define MODULE fifo_2r2w_async_simplex
|
`define MODULE fifo_2r2w_async_simplex
|
module `BASE`MODULE (
|
module `BASE`MODULE (
|
`undef MODULE
|
`undef MODULE
|
// a side
|
// a side
|
a_d, a_wr, a_fifo_full,
|
a_d, a_wr, a_fifo_full,
|
a_q, a_rd, a_fifo_empty,
|
a_q, a_rd, a_fifo_empty,
|
a_clk, a_rst,
|
a_clk, a_rst,
|
// b side
|
// b side
|
b_d, b_wr, b_fifo_full,
|
b_d, b_wr, b_fifo_full,
|
b_q, b_rd, b_fifo_empty,
|
b_q, b_rd, b_fifo_empty,
|
b_clk, b_rst
|
b_clk, b_rst
|
);
|
);
|
|
|
parameter data_width = 18;
|
parameter data_width = 18;
|
parameter addr_width = 4;
|
parameter addr_width = 4;
|
|
|
// a side
|
// a side
|
input [data_width-1:0] a_d;
|
input [data_width-1:0] a_d;
|
input a_wr;
|
input a_wr;
|
output a_fifo_full;
|
output a_fifo_full;
|
output [data_width-1:0] a_q;
|
output [data_width-1:0] a_q;
|
input a_rd;
|
input a_rd;
|
output a_fifo_empty;
|
output a_fifo_empty;
|
input a_clk;
|
input a_clk;
|
input a_rst;
|
input a_rst;
|
|
|
// b side
|
// b side
|
input [data_width-1:0] b_d;
|
input [data_width-1:0] b_d;
|
input b_wr;
|
input b_wr;
|
output b_fifo_full;
|
output b_fifo_full;
|
output [data_width-1:0] b_q;
|
output [data_width-1:0] b_q;
|
input b_rd;
|
input b_rd;
|
output b_fifo_empty;
|
output b_fifo_empty;
|
input b_clk;
|
input b_clk;
|
input b_rst;
|
input b_rst;
|
|
|
// adr_gen
|
// adr_gen
|
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
|
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
|
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
|
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
|
// dpram
|
// dpram
|
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
|
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
|
|
|
`define MODULE cnt_gray_ce_bin
|
`define MODULE cnt_gray_ce_bin
|
`BASE`MODULE
|
`BASE`MODULE
|
# ( .length(addr_width))
|
# ( .length(addr_width))
|
fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
|
fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
|
|
|
`BASE`MODULE
|
`BASE`MODULE
|
# (.length(addr_width))
|
# (.length(addr_width))
|
fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
|
fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
|
|
|
`BASE`MODULE
|
`BASE`MODULE
|
# ( .length(addr_width))
|
# ( .length(addr_width))
|
fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
|
fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
|
|
|
`BASE`MODULE
|
`BASE`MODULE
|
# (.length(addr_width))
|
# (.length(addr_width))
|
fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
|
fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
|
`undef MODULE
|
`undef MODULE
|
|
|
// mux read or write adr to DPRAM
|
// mux read or write adr to DPRAM
|
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
|
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
|
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
|
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
|
|
|
`define MODULE dpram_2r2w
|
`define MODULE dpram_2r2w
|
`BASE`MODULE
|
`BASE`MODULE
|
# (.data_width(data_width), .addr_width(addr_width+1))
|
# (.data_width(data_width), .addr_width(addr_width+1))
|
dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
|
dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
|
.d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
|
.d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
|
`undef MODULE
|
`undef MODULE
|
|
|
`define MODULE fifo_cmp_async
|
`define MODULE fifo_cmp_async
|
`BASE`MODULE
|
`BASE`MODULE
|
# (.addr_width(addr_width))
|
# (.addr_width(addr_width))
|
cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
|
cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
|
|
|
`BASE`MODULE
|
`BASE`MODULE
|
# (.addr_width(addr_width))
|
# (.addr_width(addr_width))
|
cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
|
cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
|
`undef MODULE
|
`undef MODULE
|
|
|
endmodule
|
endmodule
|
`endif
|
`endif
|
|
|
`ifdef REG_FILE
|
`ifdef REG_FILE
|
`define MODULE reg_file
|
`define MODULE reg_file
|
module `BASE`MODULE (
|
module `BASE`MODULE (
|
`undef MODULE
|
`undef MODULE
|
a1, a2, a3, wd3, we3, rd1, rd2, clk
|
a1, a2, a3, wd3, we3, rd1, rd2, clk
|
);
|
);
|
parameter data_width = 32;
|
parameter data_width = 32;
|
parameter addr_width = 5;
|
parameter addr_width = 5;
|
input [addr_width-1:0] a1, a2, a3;
|
input [addr_width-1:0] a1, a2, a3;
|
input [data_width-1:0] wd3;
|
input [data_width-1:0] wd3;
|
input we3;
|
input we3;
|
output [data_width-1:0] rd1, rd2;
|
output [data_width-1:0] rd1, rd2;
|
input clk;
|
input clk;
|
|
|
`ifdef ACTEL
|
`ifdef ACTEL
|
reg [data_width-1:0] wd3_reg;
|
reg [data_width-1:0] wd3_reg;
|
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
|
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
|
reg we3_reg;
|
reg we3_reg;
|
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN;
|
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN;
|
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] `SYN;
|
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] `SYN;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
{wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
|
{wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
|
else
|
else
|
{wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
|
{wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
|
|
|
always @ (negedge clk)
|
always @ (negedge clk)
|
if (we3_reg)
|
if (we3_reg)
|
ram1[a3_reg] <= wd3;
|
ram1[a3_reg] <= wd3;
|
always @ (posedge clk)
|
always @ (posedge clk)
|
a1_reg <= a1;
|
a1_reg <= a1;
|
assign rd1 = ram1[a1_reg];
|
assign rd1 = ram1[a1_reg];
|
|
|
always @ (negedge clk)
|
always @ (negedge clk)
|
if (we3_reg)
|
if (we3_reg)
|
ram2[a3_reg] <= wd3;
|
ram2[a3_reg] <= wd3;
|
always @ (posedge clk)
|
always @ (posedge clk)
|
a2_reg <= a2;
|
a2_reg <= a2;
|
assign rd2 = ram2[a2_reg];
|
assign rd2 = ram2[a2_reg];
|
|
|
`else
|
`else
|
|
|
`define MODULE dpram_1r1w
|
`define MODULE dpram_1r1w
|
`BASE`MODULE
|
`BASE`MODULE
|
# ( .data_width(data_width), .addr_width(addr_width))
|
# ( .data_width(data_width), .addr_width(addr_width))
|
ram1 (
|
ram1 (
|
.d_a(wd3),
|
.d_a(wd3),
|
.adr_a(a3),
|
.adr_a(a3),
|
.we_a(we3),
|
.we_a(we3),
|
.clk_a(clk),
|
.clk_a(clk),
|
.q_b(rd1),
|
.q_b(rd1),
|
.adr_b(a1),
|
.adr_b(a1),
|
.clk_b(clk) );
|
.clk_b(clk) );
|
|
|
`BASE`MODULE
|
`BASE`MODULE
|
# ( .data_width(data_width), .addr_width(addr_width))
|
# ( .data_width(data_width), .addr_width(addr_width))
|
ram2 (
|
ram2 (
|
.d_a(wd3),
|
.d_a(wd3),
|
.adr_a(a3),
|
.adr_a(a3),
|
.we_a(we3),
|
.we_a(we3),
|
.clk_a(clk),
|
.clk_a(clk),
|
.q_b(rd2),
|
.q_b(rd2),
|
.adr_b(a2),
|
.adr_b(a2),
|
.clk_b(clk) );
|
.clk_b(clk) );
|
`undef MODULE
|
`undef MODULE
|
|
|
`endif
|
`endif
|
|
|
endmodule
|
endmodule
|
`endif
|
`endif
|
|
|
