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| Rev 83 |
Rev 84 |
| Line 113... |
Line 113... |
input [(data_width/8)-1:0] be;
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input [(data_width/8)-1:0] be;
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input we;
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input we;
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output reg [(data_width-1):0] q;
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output reg [(data_width-1):0] q;
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input clk;
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input clk;
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//E2_ifdef SYSTEMVERILOG
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//E2_ifdef SYSTEMVERILOG
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logic [data_width/8-1:0][7:0] ram[0:mem_size-1];// # words = 1 << address width
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logic [data_width/8-1:0][7:0] ram[0:mem_size-1];// # words = 1 << address width
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//E2_else
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//E2_else
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reg [data_width-1:0] ram [mem_size-1:0];
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reg [data_width-1:0] ram [mem_size-1:0];
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wire [data_width/8-1:0] cke;
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//E2_endif
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//E2_endif
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parameter memory_init = 0;
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parameter memory_init = 0;
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parameter memory_file = "vl_ram.vmem";
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parameter memory_file = "vl_ram.vmem";
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generate if (memory_init) begin : init_mem
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generate if (memory_init) begin : init_mem
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q <= ram[adr];
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q <= ram[adr];
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end
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end
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//E2_else
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//E2_else
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assign cke = {data_width/8{we}} & be;
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genvar i;
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genvar i;
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generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
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generate for (i=0;i<data_width/8;i=i+1) begin : be_ram
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always @ (posedge clk)
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always @ (posedge clk)
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if (we & be[i])
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if (cke[i])
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ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
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ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
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end
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end
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endgenerate
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endgenerate
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always @ (posedge clk)
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always @ (posedge clk)
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q <= ram[adr];
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q <= ram[adr];
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//E2_endif
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//E2_endif
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// Function to access RAM (for use by Verilator).
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function [31:0] get_mem;
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// verilator public
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input [aw-1:0] addr;
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get_mem = ram[addr];
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endfunction // get_mem
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// Function to write RAM (for use by Verilator).
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function set_mem;
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// verilator public
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input [aw-1:0] addr;
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input [dw-1:0] data;
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ram[addr] = data;
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endfunction // set_mem
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endmodule
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endmodule
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`endif
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`endif
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`ifdef ACTEL
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`ifdef ACTEL
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// ACTEL FPGA should not use logic to handle rw collision
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// ACTEL FPGA should not use logic to handle rw collision
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