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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [memories.v] - Diff between revs 83 and 84

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Rev 83 Rev 84
Line 113... Line 113...
   input [(data_width/8)-1:0]    be;
   input [(data_width/8)-1:0]    be;
   input                         we;
   input                         we;
   output reg [(data_width-1):0] q;
   output reg [(data_width-1):0] q;
   input                         clk;
   input                         clk;
 
 
 
 
//E2_ifdef SYSTEMVERILOG
//E2_ifdef SYSTEMVERILOG
   logic [data_width/8-1:0][7:0] ram[0:mem_size-1];// # words = 1 << address width
   logic [data_width/8-1:0][7:0] ram[0:mem_size-1];// # words = 1 << address width
//E2_else
//E2_else
   reg [data_width-1:0] ram [mem_size-1:0];
   reg [data_width-1:0] ram [mem_size-1:0];
 
    wire [data_width/8-1:0] cke;
//E2_endif
//E2_endif
 
 
   parameter memory_init = 0;
   parameter memory_init = 0;
   parameter memory_file = "vl_ram.vmem";
   parameter memory_file = "vl_ram.vmem";
   generate if (memory_init) begin : init_mem
   generate if (memory_init) begin : init_mem
Line 146... Line 148...
    q <= ram[adr];
    q <= ram[adr];
end
end
 
 
//E2_else
//E2_else
 
 
 
assign cke = {data_width/8{we}} & be;
   genvar i;
   genvar i;
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
   generate for (i=0;i<data_width/8;i=i+1) begin : be_ram
      always @ (posedge clk)
      always @ (posedge clk)
      if (we & be[i])
      if (cke[i])
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
   end
   end
   endgenerate
   endgenerate
 
 
   always @ (posedge clk)
   always @ (posedge clk)
      q <= ram[adr];
      q <= ram[adr];
 
 
//E2_endif
//E2_endif
 
 
 
   // Function to access RAM (for use by Verilator).
 
   function [31:0] get_mem;
 
      // verilator public
 
      input [aw-1:0]             addr;
 
      get_mem = ram[addr];
 
   endfunction // get_mem
 
 
 
   // Function to write RAM (for use by Verilator).
 
   function set_mem;
 
      // verilator public
 
      input [aw-1:0]             addr;
 
      input [dw-1:0]             data;
 
      ram[addr] = data;
 
   endfunction // set_mem
 
 
endmodule
endmodule
`endif
`endif
 
 
`ifdef ACTEL
`ifdef ACTEL
        // ACTEL FPGA should not use logic to handle rw collision
        // ACTEL FPGA should not use logic to handle rw collision

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