URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [memories.v] - Diff between revs 84 and 85

Rev 84	Rev 85
Line 138...	Line 138...
`//to model individual bytes within the word`	`//to model individual bytes within the word`

`always_ff@(posedge clk)`	`always_ff@(posedge clk)`
`begin`	`begin`
`if(we) begin // note: we should have a for statement to support any bus width`	`if(we) begin // note: we should have a for statement to support any bus width`
`if(be[3]) ram[adr[addr_width-2:0]][3] <= d[31:24];`	`if(be[3]) ram[adr[3] <= d[31:24];`
`if(be[2]) ram[adr[addr_width-2:0]][2] <= d[23:16];`	`if(be[2]) ram[adr[2] <= d[23:16];`
`if(be[1]) ram[adr[addr_width-2:0]][1] <= d[15:8];`	`if(be[1]) ram[adr[1] <= d[15:8];`
`if(be[0]) ram[adr[addr_width-2:0]][0] <= d[7:0];`	`if(be[0]) ram[adr[0] <= d[7:0];`
`end`	`end`
`q <= ram[adr];`	`q <= ram[adr];`
`end`	`end`

`//E2_else`	`//E2_else`