OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [memories.v] - Diff between revs 92 and 93

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 92 Rev 93
Line 162... Line 162...
   always @ (posedge clk)
   always @ (posedge clk)
      q <= ram[adr];
      q <= ram[adr];
 
 
//E2_endif
//E2_endif
 
 
 
//E2_ifdef verilator
   // Function to access RAM (for use by Verilator).
   // Function to access RAM (for use by Verilator).
   function [31:0] get_mem;
   function [31:0] get_mem;
      // verilator public
      // verilator public
      input [addr_width-1:0]             addr;
      input [addr_width-1:0]             addr;
      get_mem = ram[addr];
      get_mem = ram[addr];
Line 176... Line 177...
      // verilator public
      // verilator public
      input [addr_width-1:0]             addr;
      input [addr_width-1:0]             addr;
      input [data_width-1:0]             data;
      input [data_width-1:0]             data;
      ram[addr] = data;
      ram[addr] = data;
   endfunction // set_mem
   endfunction // set_mem
 
//E2_endif
 
 
endmodule
endmodule
`endif
`endif
 
 
`ifdef ACTEL
`ifdef ACTEL

powered by: WebSVN 2.1.0

© copyright 1999-2021 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.