| Line 77... |
Line 77... |
input [(data_width-1):0] d;
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input [(data_width-1):0] d;
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input [(addr_width-1):0] adr;
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input [(addr_width-1):0] adr;
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input we;
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input we;
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output reg [(data_width-1):0] q;
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output reg [(data_width-1):0] q;
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input clk;
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input clk;
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reg [data_width-1:0] ram [mem_szie-1:0];
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reg [data_width-1:0] ram [mem_size-1:0];
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parameter init = 0;
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parameter init = 0;
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parameter memory_file = "vl_ram.vmem";
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parameter memory_file = "vl_ram.vmem";
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generate if (init) begin : init_mem
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generate if (init) begin : init_mem
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initial
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initial
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begin
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begin
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| Line 182... |
Line 182... |
//E2_endif
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//E2_endif
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endmodule
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endmodule
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`endif
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`endif
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`ifdef ACTEL
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// ACTEL FPGA should not use logic to handle rw collision
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`define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
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`else
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`define SYN
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`endif
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`ifdef DPRAM_1R1W
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`ifdef DPRAM_1R1W
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`define MODULE dpram_1r1w
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`define MODULE dpram_1r1w
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module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
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module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
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`undef MODULE
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`undef MODULE
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parameter data_width = 32;
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parameter data_width = 32;
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| Line 203... |
Line 196... |
input [(addr_width-1):0] adr_b;
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input [(addr_width-1):0] adr_b;
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input we_a;
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input we_a;
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output [(data_width-1):0] q_b;
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output [(data_width-1):0] q_b;
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input clk_a, clk_b;
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input clk_a, clk_b;
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reg [(addr_width-1):0] adr_b_reg;
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reg [(addr_width-1):0] adr_b_reg;
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reg [data_width-1:0] ram [mem_szie-1:0] `SYN;
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reg [data_width-1:0] ram [mem_szie-1:0] `SYN_NO_RW_CHECK;
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|
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parameter init = 0;
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parameter init = 0;
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parameter memory_file = "vl_ram.vmem";
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parameter memory_file = "vl_ram.vmem";
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generate if (init) begin : init_mem
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generate if (init) begin : init_mem
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initial
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initial
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| Line 241... |
Line 234... |
input we_a;
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input we_a;
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output [(data_width-1):0] q_b;
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output [(data_width-1):0] q_b;
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output reg [(data_width-1):0] q_a;
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output reg [(data_width-1):0] q_a;
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input clk_a, clk_b;
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input clk_a, clk_b;
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reg [(data_width-1):0] q_b;
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reg [(data_width-1):0] q_b;
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reg [data_width-1:0] ram [mem_szie-1:0] `SYN;
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reg [data_width-1:0] ram [mem_szie-1:0] `SYN_NO_RW_CHECK;
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|
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parameter init = 0;
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parameter init = 0;
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parameter memory_file = "vl_ram.vmem";
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parameter memory_file = "vl_ram.vmem";
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generate if (init) begin : init_mem
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generate if (init) begin : init_mem
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initial
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initial
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| Line 282... |
Line 275... |
input [(data_width-1):0] d_b;
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input [(data_width-1):0] d_b;
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output reg [(data_width-1):0] q_a;
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output reg [(data_width-1):0] q_a;
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input we_b;
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input we_b;
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input clk_a, clk_b;
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input clk_a, clk_b;
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reg [(data_width-1):0] q_b;
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reg [(data_width-1):0] q_b;
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reg [data_width-1:0] ram [mem_size-1:0] `SYN;
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reg [data_width-1:0] ram [mem_size-1:0] `SYN_NO_RW_CHECK;
|
|
|
parameter init = 0;
|
parameter init = 0;
|
parameter memory_file = "vl_ram.vmem";
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parameter memory_file = "vl_ram.vmem";
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generate if (init) begin : init_mem
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generate if (init) begin : init_mem
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initial
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initial
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| Line 344... |
Line 337... |
//to model individual bytes within the word
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//to model individual bytes within the word
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|
|
generate
|
generate
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if (a_data_width==32 & b_data_width==32) begin : dpram_3232
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if (a_data_width==32 & b_data_width==32) begin : dpram_3232
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|
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logic [0:3][7:0] ram [0:mem_size-1];
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logic [0:3][7:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
|
|
|
initial
|
initial
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if (init)
|
if (init)
|
$readmemh(memory_file, ram);
|
$readmemh(memory_file, ram);
|
|
|
| Line 382... |
Line 375... |
endgenerate
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endgenerate
|
|
|
generate
|
generate
|
if (a_data_width==64 & b_data_width==64) begin : dpram_6464
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if (a_data_width==64 & b_data_width==64) begin : dpram_6464
|
|
|
logic [0:7][7:0] ram [0:mem_size-1];
|
logic [0:7][7:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
|
|
|
initial
|
initial
|
if (init)
|
if (init)
|
$readmemh(memory_file, ram);
|
$readmemh(memory_file, ram);
|
|
|
| Line 487... |
Line 480... |
end
|
end
|
endgenerate
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endgenerate
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|
|
//E2_else
|
//E2_else
|
// This modules requires SystemVerilog
|
// This modules requires SystemVerilog
|
|
// at this point anyway
|
//E2_endif
|
//E2_endif
|
endmodule
|
endmodule
|
`endif
|
`endif
|
|
|
`ifdef CAM
|
`ifdef CAM
|
| Line 942... |
Line 936... |
|
|
`ifdef ACTEL
|
`ifdef ACTEL
|
reg [data_width-1:0] wd3_reg;
|
reg [data_width-1:0] wd3_reg;
|
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
|
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
|
reg we3_reg;
|
reg we3_reg;
|
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN;
|
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN_NO_RW_CHECK;
|
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] `SYN;
|
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] `SYN_NO_RW_CHECK;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
{wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
|
{wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
|
else
|
else
|
{wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
|
{wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
|
