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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [memories.v] - Diff between revs 95 and 98

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Rev 95 Rev 98
Line 77... Line 77...
   input [(data_width-1):0]      d;
   input [(data_width-1):0]      d;
   input [(addr_width-1):0]       adr;
   input [(addr_width-1):0]       adr;
   input                         we;
   input                         we;
   output reg [(data_width-1):0] q;
   output reg [(data_width-1):0] q;
   input                         clk;
   input                         clk;
   reg [data_width-1:0] ram [mem_szie-1:0];
   reg [data_width-1:0] ram [mem_size-1:0];
   parameter init = 0;
   parameter init = 0;
   parameter memory_file = "vl_ram.vmem";
   parameter memory_file = "vl_ram.vmem";
   generate if (init) begin : init_mem
   generate if (init) begin : init_mem
   initial
   initial
     begin
     begin
Line 182... Line 182...
//E2_endif
//E2_endif
 
 
endmodule
endmodule
`endif
`endif
 
 
`ifdef ACTEL
 
        // ACTEL FPGA should not use logic to handle rw collision
 
        `define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
 
`else
 
        `define SYN
 
`endif
 
 
 
`ifdef DPRAM_1R1W
`ifdef DPRAM_1R1W
`define MODULE dpram_1r1w
`define MODULE dpram_1r1w
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
`undef MODULE
`undef MODULE
   parameter data_width = 32;
   parameter data_width = 32;
Line 203... Line 196...
   input [(addr_width-1):0]       adr_b;
   input [(addr_width-1):0]       adr_b;
   input                         we_a;
   input                         we_a;
   output [(data_width-1):0]      q_b;
   output [(data_width-1):0]      q_b;
   input                         clk_a, clk_b;
   input                         clk_a, clk_b;
   reg [(addr_width-1):0]         adr_b_reg;
   reg [(addr_width-1):0]         adr_b_reg;
   reg [data_width-1:0] ram [mem_szie-1:0] `SYN;
   reg [data_width-1:0] ram [mem_szie-1:0] `SYN_NO_RW_CHECK;
 
 
   parameter init = 0;
   parameter init = 0;
   parameter memory_file = "vl_ram.vmem";
   parameter memory_file = "vl_ram.vmem";
   generate if (init) begin : init_mem
   generate if (init) begin : init_mem
   initial
   initial
Line 241... Line 234...
   input                         we_a;
   input                         we_a;
   output [(data_width-1):0]      q_b;
   output [(data_width-1):0]      q_b;
   output reg [(data_width-1):0] q_a;
   output reg [(data_width-1):0] q_a;
   input                         clk_a, clk_b;
   input                         clk_a, clk_b;
   reg [(data_width-1):0]         q_b;
   reg [(data_width-1):0]         q_b;
   reg [data_width-1:0] ram [mem_szie-1:0] `SYN;
   reg [data_width-1:0] ram [mem_szie-1:0] `SYN_NO_RW_CHECK;
 
 
   parameter init = 0;
   parameter init = 0;
   parameter memory_file = "vl_ram.vmem";
   parameter memory_file = "vl_ram.vmem";
   generate if (init) begin : init_mem
   generate if (init) begin : init_mem
   initial
   initial
Line 282... Line 275...
   input [(data_width-1):0]       d_b;
   input [(data_width-1):0]       d_b;
   output reg [(data_width-1):0] q_a;
   output reg [(data_width-1):0] q_a;
   input                         we_b;
   input                         we_b;
   input                         clk_a, clk_b;
   input                         clk_a, clk_b;
   reg [(data_width-1):0]         q_b;
   reg [(data_width-1):0]         q_b;
   reg [data_width-1:0] ram [mem_size-1:0] `SYN;
   reg [data_width-1:0] ram [mem_size-1:0] `SYN_NO_RW_CHECK;
 
 
   parameter init = 0;
   parameter init = 0;
   parameter memory_file = "vl_ram.vmem";
   parameter memory_file = "vl_ram.vmem";
   generate if (init) begin : init_mem
   generate if (init) begin : init_mem
   initial
   initial
Line 344... Line 337...
//to model individual bytes within the word
//to model individual bytes within the word
 
 
generate
generate
if (a_data_width==32 & b_data_width==32) begin : dpram_3232
if (a_data_width==32 & b_data_width==32) begin : dpram_3232
 
 
    logic [0:3][7:0] ram [0:mem_size-1];
    logic [0:3][7:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
 
 
    initial
    initial
        if (init)
        if (init)
            $readmemh(memory_file, ram);
            $readmemh(memory_file, ram);
 
 
Line 382... Line 375...
endgenerate
endgenerate
 
 
generate
generate
if (a_data_width==64 & b_data_width==64) begin : dpram_6464
if (a_data_width==64 & b_data_width==64) begin : dpram_6464
 
 
    logic [0:7][7:0] ram [0:mem_size-1];
    logic [0:7][7:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
 
 
    initial
    initial
        if (init)
        if (init)
            $readmemh(memory_file, ram);
            $readmemh(memory_file, ram);
 
 
Line 487... Line 480...
end
end
endgenerate
endgenerate
 
 
//E2_else
//E2_else
    // This modules requires SystemVerilog
    // This modules requires SystemVerilog
 
    // at this point anyway
//E2_endif
//E2_endif
endmodule
endmodule
`endif
`endif
 
 
`ifdef CAM
`ifdef CAM
Line 942... Line 936...
 
 
`ifdef ACTEL
`ifdef ACTEL
reg [data_width-1:0] wd3_reg;
reg [data_width-1:0] wd3_reg;
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
reg we3_reg;
reg we3_reg;
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN;
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN_NO_RW_CHECK;
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] `SYN;
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] `SYN_NO_RW_CHECK;
always @ (posedge clk or posedge rst)
always @ (posedge clk or posedge rst)
if (rst)
if (rst)
    {wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
    {wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
else
else
    {wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
    {wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};

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