//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Versatile library, registers ////
|
//// Versatile library, registers ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
//// Different type of registers ////
|
//// Different type of registers ////
|
//// ////
|
//// ////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
//// - add more different registers ////
|
//// - add more different registers ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// ORSoC AB ////
|
//// ORSoC AB ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
|
|
module dff ( d, q, clk, rst);
|
module dff ( d, q, clk, rst);
|
|
|
parameter width = 1;
|
parameter width = 1;
|
parameter reset_value = 0;
|
parameter reset_value = 0;
|
|
|
input [width-1:0] d;
|
input [width-1:0] d;
|
input clk, rst;
|
input clk, rst;
|
output reg [width-1:0] q;
|
output reg [width-1:0] q;
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
q <= reset_value;
|
q <= reset_value;
|
else
|
else
|
q <= d;
|
q <= d;
|
|
|
endmodule
|
endmodule
|
|
|
module dff_array ( d, q, clk, rst);
|
module dff_array ( d, q, clk, rst);
|
|
|
parameter width = 1;
|
parameter width = 1;
|
parameter depth = 2;
|
parameter depth = 2;
|
parameter reset_value = 1'b0;
|
parameter reset_value = 1'b0;
|
|
|
input [width-1:0] d;
|
input [width-1:0] d;
|
input clk, rst;
|
input clk, rst;
|
output [width-1:0] q;
|
output [width-1:0] q;
|
reg [0:depth-1] q_tmp [width-1:0];
|
reg [0:depth-1] q_tmp [width-1:0];
|
integer i;
|
integer i;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst) begin
|
if (rst) begin
|
for (i=0;i<depth;i=i+1)
|
for (i=0;i<depth;i=i+1)
|
q_tmp[i] <= {width{reset_value}};
|
q_tmp[i] <= {width{reset_value}};
|
end else begin
|
end else begin
|
q_tmp[0] <= d;
|
q_tmp[0] <= d;
|
for (i=1;i<depth;i=i+1)
|
for (i=1;i<depth;i=i+1)
|
q_tmp[i] <= q_tmp[i-1];
|
q_tmp[i] <= q_tmp[i-1];
|
end
|
end
|
|
|
assign q = q_tmp[depth-1];
|
assign q = q_tmp[depth-1];
|
|
|
endmodule
|
endmodule
|
|
|
module dff_ce ( d, ce, q, clk, rst);
|
module dff_ce ( d, ce, q, clk, rst);
|
|
|
parameter width = 1;
|
parameter width = 1;
|
parameter reset_value = 0;
|
parameter reset_value = 0;
|
|
|
input [width-1:0] d;
|
input [width-1:0] d;
|
input ce, clk, rst;
|
input ce, clk, rst;
|
output reg [width-1:0] q;
|
output reg [width-1:0] q;
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
q <= reset_value;
|
q <= reset_value;
|
else
|
else
|
if (ce)
|
if (ce)
|
q <= d;
|
q <= d;
|
|
|
endmodule
|
endmodule
|
|
|
module dff_ce_clear ( d, ce, clear, q, clk, rst);
|
module dff_ce_clear ( d, ce, clear, q, clk, rst);
|
|
|
parameter width = 1;
|
parameter width = 1;
|
parameter reset_value = 0;
|
parameter reset_value = 0;
|
|
|
input [width-1:0] d;
|
input [width-1:0] d;
|
input ce, clk, rst;
|
input ce, clear, clk, rst;
|
output reg [width-1:0] q;
|
output reg [width-1:0] q;
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
q <= reset_value;
|
q <= reset_value;
|
else
|
else
|
if (ce)
|
if (ce)
|
if (clear)
|
if (clear)
|
q <= {width{1'b0}};
|
q <= {width{1'b0}};
|
else
|
else
|
q <= d;
|
q <= d;
|
|
|
endmodule
|
endmodule
|
|
|
`ifdef ALTERA
|
`ifdef ALTERA
|
// megafunction wizard: %LPM_FF%
|
// megafunction wizard: %LPM_FF%
|
// GENERATION: STANDARD
|
// GENERATION: STANDARD
|
// VERSION: WM1.0
|
// VERSION: WM1.0
|
// MODULE: lpm_ff
|
// MODULE: lpm_ff
|
|
|
// ============================================================
|
// ============================================================
|
// File Name: dff_sr.v
|
// File Name: dff_sr.v
|
// Megafunction Name(s):
|
// Megafunction Name(s):
|
// lpm_ff
|
// lpm_ff
|
//
|
//
|
// Simulation Library Files(s):
|
// Simulation Library Files(s):
|
// lpm
|
// lpm
|
// ============================================================
|
// ============================================================
|
// ************************************************************
|
// ************************************************************
|
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
//
|
//
|
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
|
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
|
// ************************************************************
|
// ************************************************************
|
|
|
|
|
//Copyright (C) 1991-2010 Altera Corporation
|
//Copyright (C) 1991-2010 Altera Corporation
|
//Your use of Altera Corporation's design tools, logic functions
|
//Your use of Altera Corporation's design tools, logic functions
|
//and other software and tools, and its AMPP partner logic
|
//and other software and tools, and its AMPP partner logic
|
//functions, and any output files from any of the foregoing
|
//functions, and any output files from any of the foregoing
|
//(including device programming or simulation files), and any
|
//(including device programming or simulation files), and any
|
//associated documentation or information are expressly subject
|
//associated documentation or information are expressly subject
|
//to the terms and conditions of the Altera Program License
|
//to the terms and conditions of the Altera Program License
|
//Subscription Agreement, Altera MegaCore Function License
|
//Subscription Agreement, Altera MegaCore Function License
|
//Agreement, or other applicable license agreement, including,
|
//Agreement, or other applicable license agreement, including,
|
//without limitation, that your use is for the sole purpose of
|
//without limitation, that your use is for the sole purpose of
|
//programming logic devices manufactured by Altera and sold by
|
//programming logic devices manufactured by Altera and sold by
|
//Altera or its authorized distributors. Please refer to the
|
//Altera or its authorized distributors. Please refer to the
|
//applicable agreement for further details.
|
//applicable agreement for further details.
|
|
|
|
|
// synopsys translate_off
|
// synopsys translate_off
|
`timescale 1 ps / 1 ps
|
`timescale 1 ps / 1 ps
|
// synopsys translate_on
|
// synopsys translate_on
|
module dff_sr (
|
module dff_sr (
|
aclr,
|
aclr,
|
aset,
|
aset,
|
clock,
|
clock,
|
data,
|
data,
|
q);
|
q);
|
|
|
input aclr;
|
input aclr;
|
input aset;
|
input aset;
|
input clock;
|
input clock;
|
input data;
|
input data;
|
output q;
|
output q;
|
|
|
wire [0:0] sub_wire0;
|
wire [0:0] sub_wire0;
|
wire [0:0] sub_wire1 = sub_wire0[0:0];
|
wire [0:0] sub_wire1 = sub_wire0[0:0];
|
wire q = sub_wire1;
|
wire q = sub_wire1;
|
wire sub_wire2 = data;
|
wire sub_wire2 = data;
|
wire sub_wire3 = sub_wire2;
|
wire sub_wire3 = sub_wire2;
|
|
|
lpm_ff lpm_ff_component (
|
lpm_ff lpm_ff_component (
|
.aclr (aclr),
|
.aclr (aclr),
|
.clock (clock),
|
.clock (clock),
|
.data (sub_wire3),
|
.data (sub_wire3),
|
.aset (aset),
|
.aset (aset),
|
.q (sub_wire0)
|
.q (sub_wire0)
|
// synopsys translate_off
|
// synopsys translate_off
|
,
|
,
|
.aload (),
|
.aload (),
|
.enable (),
|
.enable (),
|
.sclr (),
|
.sclr (),
|
.sload (),
|
.sload (),
|
.sset ()
|
.sset ()
|
// synopsys translate_on
|
// synopsys translate_on
|
);
|
);
|
defparam
|
defparam
|
lpm_ff_component.lpm_fftype = "DFF",
|
lpm_ff_component.lpm_fftype = "DFF",
|
lpm_ff_component.lpm_type = "LPM_FF",
|
lpm_ff_component.lpm_type = "LPM_FF",
|
lpm_ff_component.lpm_width = 1;
|
lpm_ff_component.lpm_width = 1;
|
|
|
|
|
endmodule
|
endmodule
|
|
|
// ============================================================
|
// ============================================================
|
// CNX file retrieval info
|
// CNX file retrieval info
|
// ============================================================
|
// ============================================================
|
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
|
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
|
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
|
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
|
// Retrieval info: PRIVATE: ASET NUMERIC "1"
|
// Retrieval info: PRIVATE: ASET NUMERIC "1"
|
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
|
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
|
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
|
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
|
// Retrieval info: PRIVATE: DFF NUMERIC "1"
|
// Retrieval info: PRIVATE: DFF NUMERIC "1"
|
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
|
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
|
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
|
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
|
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
|
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
|
// Retrieval info: PRIVATE: SSET NUMERIC "0"
|
// Retrieval info: PRIVATE: SSET NUMERIC "0"
|
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
|
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
|
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
|
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
|
// Retrieval info: PRIVATE: nBit NUMERIC "1"
|
// Retrieval info: PRIVATE: nBit NUMERIC "1"
|
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
|
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
|
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
|
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
|
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
|
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
|
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
|
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
|
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
|
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
|
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
|
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
|
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
|
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
|
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
|
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
|
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
|
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
|
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
|
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
|
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
|
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
|
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
|
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
|
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
|
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
|
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
|
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
|
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
|
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
|
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
|
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
|
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
|
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
|
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
|
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
|
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
|
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
|
// Retrieval info: LIB_FILE: lpm
|
// Retrieval info: LIB_FILE: lpm
|
|
|
|
|
`else
|
`else
|
|
|
|
|
module dff_sr ( aclr, aset, clock, data, q);
|
module dff_sr ( aclr, aset, clock, data, q);
|
|
|
input aclr;
|
input aclr;
|
input aset;
|
input aset;
|
input clock;
|
input clock;
|
input data;
|
input data;
|
output reg q;
|
output reg q;
|
|
|
always @ (posedge clock or posedge aclr or posedge aset)
|
always @ (posedge clock or posedge aclr or posedge aset)
|
if (aclr)
|
if (aclr)
|
q <= 1'b0;
|
q <= 1'b0;
|
else if (aset)
|
else if (aset)
|
q <= 1'b1;
|
q <= 1'b1;
|
else
|
else
|
q <= data;
|
q <= data;
|
|
|
endmodule
|
endmodule
|
|
|
`endif
|
`endif
|
|
|
// LATCH
|
// LATCH
|
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
|
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
|
`ifdef ALTERA
|
`ifdef ALTERA
|
module latch ( d, le, q, clk);
|
module latch ( d, le, q, clk);
|
input d, le;
|
input d, le;
|
output q;
|
output q;
|
input clk;
|
input clk;
|
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
|
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
|
endmodule
|
endmodule
|
`else
|
`else
|
module latch ( d, le, q, clk);
|
module latch ( d, le, q, clk);
|
input d, le;
|
input d, le;
|
output q;
|
output q;
|
input clk;/*
|
input clk;/*
|
always @ (posedge direction_set or posedge direction_clr)
|
always @ (posedge direction_set or posedge direction_clr)
|
if (direction_clr)
|
if (direction_clr)
|
direction <= going_empty;
|
direction <= going_empty;
|
else
|
else
|
direction <= going_full;*/
|
direction <= going_full;*/
|
endmodule
|
endmodule
|
|
|
