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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [registers.v] - Diff between revs 10 and 15

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Rev 10 Rev 15
Line 284... Line 284...
       direction <= going_empty;
       direction <= going_empty;
     else
     else
       direction <= going_full;*/
       direction <= going_full;*/
endmodule
endmodule
`endif
`endif
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module delay ( d, q, clk, rst);
 
parameter depth = 10;
 
input d;
 
output q;
 
input clk, rst;
 
 
 
reg [1:depth] dffs;
 
 
 
always @ (posedge clk or posedge rst)
 
if (rst)
 
    dffs <= {depth{1'b0}};
 
else
 
    dffs <= {d,dffs[1:depth-1]};
 
assign q = dffs[depth];
 
endmodule
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