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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [registers.v] - Diff between revs 24 and 29

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Rev 24 Rev 29
Line 140... Line 140...
                else
                else
                    q <= d;
                    q <= d;
 
 
endmodule
endmodule
 
 
 
module vl_spr ( sp, r, q, clk, rst);
 
 
 
        parameter width = 1;
 
        parameter reset_value = 0;
 
 
 
        input sp, r;
 
        output reg q;
 
        input clk, rst;
 
 
 
        always @ (posedge clk or posedge rst)
 
        if (rst)
 
            q <= reset_value;
 
        else
 
            if (sp)
 
                q <= 1'b1;
 
            else if (r)
 
                q <= 1'b0;
 
 
 
endmodule
 
 
 
module vl_srp ( s, rp, q, clk, rst);
 
 
 
        parameter width = 1;
 
        parameter reset_value = 0;
 
 
 
        input s, rp;
 
        output reg q;
 
        input clk, rst;
 
 
 
        always @ (posedge clk or posedge rst)
 
        if (rst)
 
            q <= reset_value;
 
        else
 
            if (rp)
 
                q <= 1'b0;
 
            else if (s)
 
                q <= 1'b1;
 
 
 
endmodule
 
 
 
 
`ifdef ALTERA
`ifdef ALTERA
// megafunction wizard: %LPM_FF%
// megafunction wizard: %LPM_FF%
// GENERATION: STANDARD
// GENERATION: STANDARD
// VERSION: WM1.0
// VERSION: WM1.0
// MODULE: lpm_ff 
// MODULE: lpm_ff 

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