| Line 473... |
Line 473... |
assign q = dffs[depth];
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assign q = dffs[depth];
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assign emptyflag = !(|dffs);
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assign emptyflag = !(|dffs);
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endmodule
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endmodule
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`endif
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`endif
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`ifdef ASYNC_REG_REQ_ACK
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`ifdef PULSE2TOGGLE
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`define MODULE async_reg_req_ack
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`define MODULE pules2toggle
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module `BASE`MODULE ( d, q, req_i, req_o, ack_i, ack_o, clk_a, rst_a, clk_b, rst_b);
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module `BASE`MODULE ( pl, q, clk, rst)
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`undef MODULE
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`undef MODULE
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parameter data_width = 8;
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input pl;
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input [data_width-1:0] d;
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output q;
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output [data_width-1:0] q;
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input clk, rst;
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input req_i;
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input
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output req_o;
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always @ (posedge clk or posedge rst)
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input ack_i;
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if (rst)
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output ack_o;
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q <= 1'b0;
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input clk_a, rst_a, clk_b, rst_b;
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reg [3:0] reqi; // 3: last req in clk_a, 2: input dff, 1-0: sync
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wire rst;
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always @ (posedge clk_a or rst_a)
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if (rst_a)
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q <= {data_width{1'b0}};
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else
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else
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if (req_i)
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q <= pl ^ q;
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q <= d;
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endmodule
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`endif
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assign rst = ack_i | rst_a;
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`ifdef TOGGLE2PULSE
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always @ (posedge clk_a or posedge rst)
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`define MODULE toggle2pulse;
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module `BASE`MODULE (d, pl, clk, rst);
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input d;
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output pl;
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input clk, rst;
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reg dff;
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always @ (posedge clk or posedge rst)
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if (rst)
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if (rst)
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req[2] <= 1'b0;
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dff <= 1'b0;
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else
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else
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req[2] <= req_i & !ack_o;
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dff <= d;
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assign d ^ dff;
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endmodule
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`endif
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always @ (posedge clk_a or posedge rst_a)
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`ifdef SYNCHRONIZER
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if (rst_a)
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`define MODULE synchronizer
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req[3] <= 1'b0;
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module `BASE`MODULE (d, q, clk, rst);
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`undef MODULE
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input d;
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output reg q;
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output clk, rst;
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reg dff;
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always @ (posedge clk or posedge rst)
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if (rst)
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{dff,q} <= 2'b00;
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else
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else
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req[3] <= req[2];
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{dff,q} <= {d,dff};
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endmodule
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`endif
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always @ (posedge clk_b or posedge rst_b)
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`ifdef CDC
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if (rst_b)
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`define MODULE cdc
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req[1:0] <= 2'b00;
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module `BASE`MODULE ( start_pl, take_it_pl, take_it_grant_pl, got_it_pl, clk_src, rst_src, clk_dst, rst_dst)
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else
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`undef MODULE
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if (ack_i)
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input start_pl;
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req[1:0] <= 2'b00;
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output take_it_pl;
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else
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input take_it_grant_pl; // note: connect to take_it_pl to generate automatic ack
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req[1:0] <= req[2:1];
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output got_it_pl;
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assign req_o = req[0];
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input clk_src, rst_src;
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input clk_dst, rst_dst;
|
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wire take_it_tg, take_it_tg_sync;
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wire got_it_tg, got_it_tg_sync;
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// src -> dst
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`define MODULE pulse2toggle
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`BASE`MODULE p2t0 (
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`undef MODULE
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.pl(start_pl),
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.q(take_it_tg),
|
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.clk(clk_src),
|
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.rst(rst_src));
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|
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always @ (posedge clk_a or posedge rst_a)
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`define MODULE synchronizer
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if (rst_a)
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`BASE`MODULE sync0 (
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ack_o <= 1'b0;
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`undef MODULE
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else
|
.d(take_it_tg),
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ack_o <= req[3] & req[2];
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.q(take_it_tg_sync),
|
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.clk(clk_dst),
|
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.rst(rst_dst));
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|
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`define MODULE toggle2pulse
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`BASE`MODULE t2p0 (
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`undef MODULE
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.d(take_it_sync),
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.pl(take_it_pl),
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.clk(clk_dst),
|
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.rst(rst_dst));
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|
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// dst -> src
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`define MODULE pulse2toggle
|
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`BASE`MODULE p2t0 (
|
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`undef MODULE
|
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.pl(take_it_grant_pl),
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.q(got_it_tg),
|
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.clk(clk_dst),
|
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.rst(rst_dst));
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|
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`define MODULE synchronizer
|
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`BASE`MODULE sync1 (
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`undef MODULE
|
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.d(got_it_tg),
|
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.q(got_it_tg_sync),
|
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.clk(clk_src),
|
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.rst(rst_src));
|
|
|
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`define MODULE toggle2pulse
|
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`BASE`MODULE t2p1 (
|
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`undef MODULE
|
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.d(take_it_grant_tg_sync),
|
|
.pl(got_it_pl),
|
|
.clk(clk_src),
|
|
.rst(rst_src));
|
|
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endmodule
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endmodule
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`endif
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`endif
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