URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Diff between revs 110 and 111

Rev 110	Rev 111
Line 4342...	Line 4342...

`generate`	`generate`
`if (a_data_width==32 & b_data_width==16) begin : dpram_3216`	`if (a_data_width==32 & b_data_width==16) begin : dpram_3216`
`logic [31:0] temp;`	`logic [31:0] temp;`
`define MODULE dpram_be_2r2w	`define MODULE dpram_be_2r2w
`BASE`MODULE # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .init(memory_init), .memory_file(memory_file))	`BASE`MODULE # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file))
`undef MODULE	`undef MODULE
`dpram6464 (`	`dpram6464 (`
`.d_a(d_a),`	`.d_a(d_a),`
`.q_a(q_a),`	`.q_a(q_a),`
`.adr_a(adr_a),`	`.adr_a(adr_a),`
Line 4372...	Line 4372...

`generate`	`generate`
`if (a_data_width==32 & b_data_width==64) begin : dpram_3264`	`if (a_data_width==32 & b_data_width==64) begin : dpram_3264`
`logic [63:0] temp;`	`logic [63:0] temp;`
`define MODULE dpram_be_2r2w	`define MODULE dpram_be_2r2w
`BASE`MODULE # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .init(memory_init), .memory_file(memory_file))	`BASE`MODULE # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file))
`undef MODULE	`undef MODULE
`dpram6464 (`	`dpram6464 (`
`.d_a({d_a,d_a}),`	`.d_a({d_a,d_a}),`
`.q_a(temp),`	`.q_a(temp),`
`.adr_a(adr_a[a_addr_width-1:1]),`	`.adr_a(adr_a[a_addr_width-1:1]),`