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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Diff between revs 143 and 144

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Rev 143 Rev 144
Line 5009... Line 5009...
input clk;
input clk;
 
 
generate
generate
if (debug==1) begin : debug_we
if (debug==1) begin : debug_we
    always @ (posedge clk)
    always @ (posedge clk)
        if (we)
        if (we3)
            $display ("Value %h written at register %h : time %t", d, adr, $time);
            $display ("Value %h written at register %h : time %t", d, adr, $time);
end
end
endgenerate
endgenerate
 
 
`ifdef ACTEL
`ifdef ACTEL

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