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| Rev 148 |
Rev 149 |
| Line 7369... |
Line 7369... |
input [4:0] s; // shift operand
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input [4:0] s; // shift operand
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input [1:0] opcode;
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input [1:0] opcode;
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output [31:0] dout;
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output [31:0] dout;
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parameter opcode_sll = 2'b00;
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parameter opcode_sll = 2'b00;
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//parameter opcode_srl = 2'b01;
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parameter opcode_srl = 2'b01;
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parameter opcode_sra = 2'b10;
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parameter opcode_sra = 2'b10;
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//parameter opcode_ror = 2'b11;
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parameter opcode_ror = 2'b11;
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parameter mult=0; // if set to 1 implemented based on multipliers which saves LUT
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generate
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if (mult==1) begin : impl_mult
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wire sll, sra;
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wire sll, sra;
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assign sll = opcode == opcode_sll;
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assign sll = opcode == opcode_sll;
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assign sra = opcode == opcode_sra;
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assign sra = opcode == opcode_sra;
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wire [15:1] s1;
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wire [15:1] s1;
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Line 7446... |
assign dout[7:0] = (s[4:3]==2'b00) ? tmp[0] :
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assign dout[7:0] = (s[4:3]==2'b00) ? tmp[0] :
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(sll) ? {8{1'b0}}:
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(sll) ? {8{1'b0}}:
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(s[4:3]==2'b01) ? tmp[1] :
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(s[4:3]==2'b01) ? tmp[1] :
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(s[4:3]==2'b10) ? tmp[2] :
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(s[4:3]==2'b10) ? tmp[2] :
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tmp[3];
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tmp[3];
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end else begin : impl_classic
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reg [31:0] dout;
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`ifdef SYSTEMVERILOG
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always_comb
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`else
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always @ (din or s or opcode)
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`endif
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case (opcode)
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opcode_sll: dout = din << s;
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opcode_srl: dout = din >> s;
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opcode_sra: dout = (din >> s) | ({32,din[31]}} << (6'd32-{1'b0,s}}));
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//opcode_ror: dout = not yet implemented
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default: dout = din << s;
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endcase
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end
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engenerate
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endmodule
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endmodule
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`endif
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`endif
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`ifdef LOGIC_UNIT
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`ifdef LOGIC_UNIT
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