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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Diff between revs 21 and 22

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Rev 21 Rev 22
Line 643... Line 643...
 
 
parameter width = 32;
parameter width = 32;
parameter nr_of_ports = 4;
parameter nr_of_ports = 4;
input [width-1:0] a3, a2, a1, a0;
input [width-1:0] a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
input [nr_of_ports-1:0] sel;
output reg [width-1:0] dout;
output [width-1:0] dout;
 
 
wire [width-1:0] tmp [nr_of_ports-1:0];
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
integer i;
 
 
// and
// and
Line 665... Line 665...
 
 
parameter width = 32;
parameter width = 32;
parameter nr_of_ports = 5;
parameter nr_of_ports = 5;
input [width-1:0] a4, a3, a2, a1, a0;
input [width-1:0] a4, a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
input [nr_of_ports-1:0] sel;
output reg [width-1:0] dout;
output [width-1:0] dout;
 
 
wire [width-1:0] tmp [nr_of_ports-1:0];
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
integer i;
 
 
// and
// and
Line 688... Line 688...
 
 
parameter width = 32;
parameter width = 32;
parameter nr_of_ports = 6;
parameter nr_of_ports = 6;
input [width-1:0] a5, a4, a3, a2, a1, a0;
input [width-1:0] a5, a4, a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
input [nr_of_ports-1:0] sel;
output reg [width-1:0] dout;
output [width-1:0] dout;
 
 
wire [width-1:0] tmp [nr_of_ports-1:0];
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
integer i;
 
 
// and
// and
Line 748... Line 748...
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
// binary counter
// binary counter
 
module vl_cnt_bin ( q, rst, clk);
 
 
 
   parameter length = 4;
 
   output [length:1] q;
 
   input rst;
 
   input clk;
 
 
 
   parameter clear_value = 0;
 
   parameter set_value = 1;
 
   parameter wrap_value = 0;
 
   parameter level1_value = 15;
 
 
 
   reg  [length:1] qi;
 
   wire [length:1] q_next;
 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
 
 
 
   always @ (posedge clk or posedge rst)
 
     if (rst)
 
       qi <= {length{1'b0}};
 
     else
 
       qi <= q_next;
 
 
 
   assign q = qi;
 
 
 
endmodule
 
//////////////////////////////////////////////////////////////////////
 
////                                                              ////
 
////  Versatile counter                                           ////
 
////                                                              ////
 
////  Description                                                 ////
 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
 
////  counter                                                     ////
 
////                                                              ////
 
////  To Do:                                                      ////
 
////   - add LFSR with more taps                                  ////
 
////                                                              ////
 
////  Author(s):                                                  ////
 
////      - Michael Unneback, unneback@opencores.org              ////
 
////        ORSoC AB                                              ////
 
////                                                              ////
 
//////////////////////////////////////////////////////////////////////
 
////                                                              ////
 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
 
////                                                              ////
 
//// This source file may be used and distributed without         ////
 
//// restriction provided that this copyright statement is not    ////
 
//// removed from the file and that any derivative work contains  ////
 
//// the original copyright notice and the associated disclaimer. ////
 
////                                                              ////
 
//// This source file is free software; you can redistribute it   ////
 
//// and/or modify it under the terms of the GNU Lesser General   ////
 
//// Public License as published by the Free Software Foundation; ////
 
//// either version 2.1 of the License, or (at your option) any   ////
 
//// later version.                                               ////
 
////                                                              ////
 
//// This source is distributed in the hope that it will be       ////
 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
 
//// details.                                                     ////
 
////                                                              ////
 
//// You should have received a copy of the GNU Lesser General    ////
 
//// Public License along with this source; if not, download it   ////
 
//// from http://www.opencores.org/lgpl.shtml                     ////
 
////                                                              ////
 
//////////////////////////////////////////////////////////////////////
 
 
 
// binary counter
 
module vl_cnt_bin_clear ( clear, q, rst, clk);
 
 
 
   parameter length = 4;
 
   input clear;
 
   output [length:1] q;
 
   input rst;
 
   input clk;
 
 
 
   parameter clear_value = 0;
 
   parameter set_value = 1;
 
   parameter wrap_value = 0;
 
   parameter level1_value = 15;
 
 
 
   reg  [length:1] qi;
 
   wire [length:1] q_next;
 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
 
 
 
   always @ (posedge clk or posedge rst)
 
     if (rst)
 
       qi <= {length{1'b0}};
 
     else
 
       qi <= q_next;
 
 
 
   assign q = qi;
 
 
 
endmodule
 
//////////////////////////////////////////////////////////////////////
 
////                                                              ////
 
////  Versatile counter                                           ////
 
////                                                              ////
 
////  Description                                                 ////
 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
 
////  counter                                                     ////
 
////                                                              ////
 
////  To Do:                                                      ////
 
////   - add LFSR with more taps                                  ////
 
////                                                              ////
 
////  Author(s):                                                  ////
 
////      - Michael Unneback, unneback@opencores.org              ////
 
////        ORSoC AB                                              ////
 
////                                                              ////
 
//////////////////////////////////////////////////////////////////////
 
////                                                              ////
 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
 
////                                                              ////
 
//// This source file may be used and distributed without         ////
 
//// restriction provided that this copyright statement is not    ////
 
//// removed from the file and that any derivative work contains  ////
 
//// the original copyright notice and the associated disclaimer. ////
 
////                                                              ////
 
//// This source file is free software; you can redistribute it   ////
 
//// and/or modify it under the terms of the GNU Lesser General   ////
 
//// Public License as published by the Free Software Foundation; ////
 
//// either version 2.1 of the License, or (at your option) any   ////
 
//// later version.                                               ////
 
////                                                              ////
 
//// This source is distributed in the hope that it will be       ////
 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
 
//// details.                                                     ////
 
////                                                              ////
 
//// You should have received a copy of the GNU Lesser General    ////
 
//// Public License along with this source; if not, download it   ////
 
//// from http://www.opencores.org/lgpl.shtml                     ////
 
////                                                              ////
 
//////////////////////////////////////////////////////////////////////
 
 
 
// binary counter
module vl_cnt_bin_ce ( cke, q, rst, clk);
module vl_cnt_bin_ce ( cke, q, rst, clk);
 
 
   parameter length = 4;
   parameter length = 4;
   input cke;
   input cke;
   output [length:1] q;
   output [length:1] q;
Line 1240... Line 1377...
 
 
 
 
   always @ (posedge clk or posedge rst)
   always @ (posedge clk or posedge rst)
     if (rst)
     if (rst)
       zq <= 1'b1;
       zq <= 1'b1;
 
     else
 
     if (cke)
 
       zq <= q_next == {length{1'b0}};
 
endmodule
 
//////////////////////////////////////////////////////////////////////
 
////                                                              ////
 
////  Versatile counter                                           ////
 
////                                                              ////
 
////  Description                                                 ////
 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
 
////  counter                                                     ////
 
////                                                              ////
 
////  To Do:                                                      ////
 
////   - add LFSR with more taps                                  ////
 
////                                                              ////
 
////  Author(s):                                                  ////
 
////      - Michael Unneback, unneback@opencores.org              ////
 
////        ORSoC AB                                              ////
 
////                                                              ////
 
//////////////////////////////////////////////////////////////////////
 
////                                                              ////
 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
 
////                                                              ////
 
//// This source file may be used and distributed without         ////
 
//// restriction provided that this copyright statement is not    ////
 
//// removed from the file and that any derivative work contains  ////
 
//// the original copyright notice and the associated disclaimer. ////
 
////                                                              ////
 
//// This source file is free software; you can redistribute it   ////
 
//// and/or modify it under the terms of the GNU Lesser General   ////
 
//// Public License as published by the Free Software Foundation; ////
 
//// either version 2.1 of the License, or (at your option) any   ////
 
//// later version.                                               ////
 
////                                                              ////
 
//// This source is distributed in the hope that it will be       ////
 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
 
//// details.                                                     ////
 
////                                                              ////
 
//// You should have received a copy of the GNU Lesser General    ////
 
//// Public License along with this source; if not, download it   ////
 
//// from http://www.opencores.org/lgpl.shtml                     ////
 
////                                                              ////
 
//////////////////////////////////////////////////////////////////////
 
 
 
// LFSR counter
 
module vl_cnt_lfsr_ce_q_zq ( cke, q, zq, rst, clk);
 
 
 
   parameter length = 4;
 
   input cke;
 
   output [length:1] q;
 
   output reg zq;
 
   input rst;
 
   input clk;
 
 
 
   parameter clear_value = 0;
 
   parameter set_value = 1;
 
   parameter wrap_value = 8;
 
   parameter level1_value = 15;
 
 
 
   reg  [length:1] qi;
 
   reg lfsr_fb;
 
   wire [length:1] q_next;
 
   reg [32:1] polynom;
 
   integer i;
 
 
 
   always @ (qi)
 
   begin
 
        case (length)
 
         2: polynom = 32'b11;                               // 0x3
 
         3: polynom = 32'b110;                              // 0x6
 
         4: polynom = 32'b1100;                             // 0xC
 
         5: polynom = 32'b10100;                            // 0x14
 
         6: polynom = 32'b110000;                           // 0x30
 
         7: polynom = 32'b1100000;                          // 0x60
 
         8: polynom = 32'b10111000;                         // 0xb8
 
         9: polynom = 32'b100010000;                        // 0x110
 
        10: polynom = 32'b1001000000;                       // 0x240
 
        11: polynom = 32'b10100000000;                      // 0x500
 
        12: polynom = 32'b100000101001;                     // 0x829
 
        13: polynom = 32'b1000000001100;                    // 0x100C
 
        14: polynom = 32'b10000000010101;                   // 0x2015
 
        15: polynom = 32'b110000000000000;                  // 0x6000
 
        16: polynom = 32'b1101000000001000;                 // 0xD008
 
        17: polynom = 32'b10010000000000000;                // 0x12000
 
        18: polynom = 32'b100000010000000000;               // 0x20400
 
        19: polynom = 32'b1000000000000100011;              // 0x40023
 
        20: polynom = 32'b10000010000000000000;             // 0x82000
 
        21: polynom = 32'b101000000000000000000;            // 0x140000
 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
 
        default: polynom = 32'b0;
 
        endcase
 
        lfsr_fb = qi[length];
 
        for (i=length-1; i>=1; i=i-1) begin
 
            if (polynom[i])
 
                lfsr_fb = lfsr_fb  ~^ qi[i];
 
        end
 
    end
 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
 
 
 
   always @ (posedge clk or posedge rst)
 
     if (rst)
 
       qi <= {length{1'b0}};
 
     else
 
     if (cke)
 
       qi <= q_next;
 
 
 
   assign q = qi;
 
 
 
 
 
   always @ (posedge clk or posedge rst)
 
     if (rst)
 
       zq <= 1'b1;
     else
     else
     if (cke)
     if (cke)
       zq <= q_next == {length{1'b0}};
       zq <= q_next == {length{1'b0}};
endmodule
endmodule
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////

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