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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Diff between revs 51 and 52

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Line 4641... Line 4641...
// WB RAM with byte enable
// WB RAM with byte enable
`define MODULE wb_b4_ram_be
`define MODULE wb_b4_ram_be
module `BASE`MODULE (
module `BASE`MODULE (
`undef MODULE
`undef MODULE
    wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
    wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
    wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
    wb_dat_o, wb_stall_o, wb_ack_o, wb_clk, wb_rst);
 
 
    parameter dat_width = 32;
    parameter dat_width = 32;
    parameter adr_width = 8;
    parameter adr_width = 8;
 
 
input [dat_width-1:0] wb_dat_i;
input [dat_width-1:0] wb_dat_i;
input [adr_width-1:0] wb_adr_i;
input [adr_width-1:0] wb_adr_i;
input [dat_width/8-1:0] wb_sel_i;
input [dat_width/8-1:0] wb_sel_i;
input wb_we_i, wb_stb_i, wb_cyc_i;
input wb_we_i, wb_stb_i, wb_cyc_i;
output [dat_width-1:0] wb_dat_o;
output [dat_width-1:0] wb_dat_o;
reg [dat_width-1:0] wb_dat_o;
reg [dat_width-1:0] wb_dat_o;
output stall_o;
output wb_stall_o;
output wb_ack_o;
output wb_ack_o;
reg wb_ack_o;
reg wb_ack_o;
 
reg wb_ack_o;
input wb_clk, wb_rst;
input wb_clk, wb_rst;
 
 
generate
generate
if (dat_width==32) begin
if (dat_width==32) begin
reg [7:0] ram3 [1<<(adr_width-2)-1:0];
reg [7:0] ram3 [1<<(adr_width-2)-1:0];
Line 4674... Line 4675...
        wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]};
        wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]};
    end
    end
end
end
endgenerate
endgenerate
 
 
 
always @ (posedge wb_clk or posedge wb_rst)
 
if (rst)
 
    wb_ack_o <= 1'b0;
 
else
 
    wb_ack_o <= wb_stb_i & wb_cyc_i
 
 
 
assign wb_stall_o = 1'b0;
 
 
endmodule
endmodule
`endif
`endif
 
 
`ifdef WB_B4_ROM
`ifdef WB_B4_ROM
// WB ROM
// WB ROM

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