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Line 232... |
`ifdef REG_FILE
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`ifdef REG_FILE
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`ifndef DPRAM_1R1W
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`ifndef DPRAM_1R1W
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`define DPRAM_1R1W
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`define DPRAM_1R1W
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`endif
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`endif
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`endif
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`endif
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//////////////////////////////////////////////////////////////////////
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`ifdef WB_B3_RAM_BE
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`ifndef WB3_ARBITER_TYPE1
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`define WB3_ARBITER_TYPE1
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`endif
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`ifndef RAM_BE
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`define RAM_BE
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`endif
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`endif//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Versatile library, clock and reset ////
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//// Versatile library, clock and reset ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Logic related to clock and reset ////
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//// Logic related to clock and reset ////
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Line 4673... |
`ifdef WB_B3_RAM_BE
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`ifdef WB_B3_RAM_BE
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// WB RAM with byte enable
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// WB RAM with byte enable
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`define MODULE wb_b3_ram_be
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`define MODULE wb_b3_ram_be
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module `BASE`MODULE (
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module `BASE`MODULE (
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`undef MODULE
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`undef MODULE
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wb_dat_i, wb_adr_i, wb_cti_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
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wb_dat_i, wb_adr_i, wb_cti_i, wb_bte_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
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wb_dat_o, wb_ack_o, wb_clk, wb_rst);
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wb_dat_o, wb_ack_o, wb_clk, wb_rst);
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parameter nr_of_ports = 3;
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parameter nr_of_ports = 3;
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parameter wb_arbiter_type = 1;
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parameter wb_arbiter_type = 1;
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parameter adr_size = 26;
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parameter adr_size = 26;
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Line 4693... |
localparam bw = 2 * nr_of_ports;
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localparam bw = 2 * nr_of_ports;
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input [dw-1:0] wb_dat_i;
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input [dw-1:0] wb_dat_i;
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input [aw-1:0] wb_adr_i;
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input [aw-1:0] wb_adr_i;
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input [cw-1:0] wb_cti_i;
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input [cw-1:0] wb_cti_i;
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input [bw-1:0] wb_bte_i;
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input [sw-1:0] wb_sel_i;
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input [sw-1:0] wb_sel_i;
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input [nr_of_ports-1:0] wb_we_i, wb_stb_i, wb_cyc_i;
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input [nr_of_ports-1:0] wb_we_i, wb_stb_i, wb_cyc_i;
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output [dw-1:0] wb_dat_o;
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output [dw-1:0] wb_dat_o;
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reg [dw-1:0] wb_dat_o;
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reg [dw-1:0] wb_dat_o;
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output wb_ack_o;
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output wb_ack_o;
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Line 4708... |
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// local wb slave
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// local wb slave
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wire [dat_size-1:0] wbs_dat_i;
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wire [dat_size-1:0] wbs_dat_i;
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wire [adr_size-1:0] wbs_adr_i;
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wire [adr_size-1:0] wbs_adr_i;
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wire [2:0] wbs_cti_i;
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wire [2:0] wbs_cti_i;
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wire [1:0] wbs_bte_i;
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wire [(dat_size/8)-1:0] wbs_sel_i;
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wire [(dat_size/8)-1:0] wbs_sel_i;
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wire wbs_we_i, wbs_stb_i, wbs_cyc_i;
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wire wbs_we_i, wbs_stb_i, wbs_cyc_i;
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wire [dat_size-1:0] wbs_dat_o;
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wire [dat_size-1:0] wbs_dat_o;
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reg wbs_ack_o;
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reg wbs_ack_o;
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