URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Diff between revs 61 and 62

Rev 61	Rev 62
Line 95...	Line 95...
`ifndef SPR	`ifndef SPR
`define SPR	`define SPR
`endif	`endif
`endif	`endif

	`ifdef WB_B3_RAM_BE
	`ifndef WB3_ARBITER_TYPE1
	`define WB3_ARBITER_TYPE1
	`endif
	`ifndef RAM_BE
	`define RAM_BE
	`endif
	`endif

`ifdef WB3_ARBITER_TYPE1	`ifdef WB3_ARBITER_TYPE1
`ifndef SPR	`ifndef SPR
`define SPR	`define SPR
`endif	`endif
`ifndef MUX_ANDOR	`ifndef MUX_ANDOR
Line 232...	Line 241...
`ifdef REG_FILE	`ifdef REG_FILE
`ifndef DPRAM_1R1W	`ifndef DPRAM_1R1W
`define DPRAM_1R1W	`define DPRAM_1R1W
`endif	`endif
`endif	`endif
	`//////////////////////////////////////////////////////////////////////`
`ifdef WB_B3_RAM_BE
`ifndef WB3_ARBITER_TYPE1
`define WB3_ARBITER_TYPE1
`endif
`ifndef RAM_BE
`define RAM_BE
`endif
`endif//////////////////////////////////////////////////////////////////////
`//// ////`	`//// ////`
`//// Versatile library, clock and reset ////`	`//// Versatile library, clock and reset ////`
`//// ////`	`//// ////`
`//// Description ////`	`//// Description ////`
`//// Logic related to clock and reset ////`	`//// Logic related to clock and reset ////`