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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Diff between revs 64 and 65

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Rev 64 Rev 65
Line 3529... Line 3529...
   input [(addr_width/4)-1:0]    be;
   input [(addr_width/4)-1:0]    be;
   input                         we;
   input                         we;
   output reg [(data_width-1):0] q;
   output reg [(data_width-1):0] q;
   input                         clk;
   input                         clk;
 
 
 
`ifdef SYSTEMVERILOG
 
   logic [data_width/8-1:0][7:0] ram[0:1<<(addr_width-2)-1];// # words = 1 << address width
 
`else
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
 
`endif
 
 
   parameter memory_init = 0;
   parameter memory_init = 0;
   parameter memory_file = "vl_ram.vmem";
   parameter memory_file = "vl_ram.vmem";
   generate if (memory_init) begin : init_mem
   generate if (memory_init) begin : init_mem
   initial
   initial
Line 3545... Line 3549...
 
 
`ifdef SYSTEMVERILOG
`ifdef SYSTEMVERILOG
// use a multi-dimensional packed array
// use a multi-dimensional packed array
//to model individual bytes within the word
//to model individual bytes within the word
 
 
logic [dat_width/8-1:0][7:0] ram[0:1<<(adr_width-2)-1];// # words = 1 << address width
 
always_ff@(posedge clk)
always_ff@(posedge clk)
begin
begin
    if(we) begin // note: we should have a for statement to support any bus width
    if(we) begin // note: we should have a for statement to support any bus width
        if(be[3]) ram[adr[adr_size-2:0]][3] <= d[31:24];
        if(be[3]) ram[adr[addr_width-2:0]][3] <= d[31:24];
        if(be[2]) ram[adr[adr_size-2:0]][2] <= d[23:16];
        if(be[2]) ram[adr[addr_width-2:0]][2] <= d[23:16];
        if(be[1]) ram[adr[adr_size-2:0]][1] <= d[15:8];
        if(be[1]) ram[adr[addr_width-2:0]][1] <= d[15:8];
        if(be[0]) ram[adr[adr_size-2:0]][0] <= d[7:0];
        if(be[0]) ram[adr[addr_width-2:0]][0] <= d[7:0];
    end
    end
    q <= ram[raddr];
    q <= ram[adr];
end
end
 
 
`else
`else
 
 
   genvar i;
   genvar i;

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