| Line 3926... |
Line 3926... |
reg [(b_data_width-1):0] q_b;
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reg [(b_data_width-1):0] q_b;
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|
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generate
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generate
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if (a_data_width==32 & b_data_width==64) begin : inst32to64
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if (a_data_width==32 & b_data_width==64) begin : inst32to64
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|
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wire [63:0] temp;
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wire [63:0] tmp;
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`define MODULE dpram_2r2w
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`define MODULE dpram_2r2w
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`BASE`MODULE
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`BASE`MODULE
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# (.data_width(8), .addr_width(b_addr_width-3))
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# (.data_width(8), .addr_width(b_addr_width-3))
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ram0 (
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ram0 (
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.d_a(d_a[7:0]),
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.d_a(d_a[7:0]),
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| Line 4741... |
Line 4741... |
always @ (posedge wbs_clk or posedge wbs_rst)
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always @ (posedge wbs_clk or posedge wbs_rst)
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if (wbs_rst)
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if (wbs_rst)
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wbs_eoc <= 1'b0;
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wbs_eoc <= 1'b0;
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else
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else
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if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
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if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
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wbs_eoc <= wbs_bte_i==linear;
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wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_==3'b111);
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else if (wbs_eoc_alert & (a_rd | a_wr))
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else if (wbs_eoc_alert & (a_rd | a_wr))
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wbs_eoc <= 1'b1;
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wbs_eoc <= 1'b1;
|
|
|
`define MODULE cnt_shreg_ce_clear
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`define MODULE cnt_shreg_ce_clear
|
`BASE`MODULE # ( .length(16))
|
`BASE`MODULE # ( .length(16))
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| Line 4903... |
Line 4903... |
`define MODULE wb3avalon_bridge
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`define MODULE wb3avalon_bridge
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module `BASE`MODULE (
|
module `BASE`MODULE (
|
`undef MODULE
|
`undef MODULE
|
// wishbone slave side
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// wishbone slave side
|
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
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wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
|
// wishbone master side
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// avalon master side
|
readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
|
readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
|
|
|
input [31:0] wbs_dat_i;
|
input [31:0] wbs_dat_i;
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input [31:2] wbs_adr_i;
|
input [31:2] wbs_adr_i;
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input [3:0] wbs_sel_i;
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input [3:0] wbs_sel_i;
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| Line 4949... |
Line 4949... |
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o;
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assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o;
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assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o;
|
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o;
|
assign wbm_ack_i = (readdatavalid & !waitrequest) | (write & !waitrequest);
|
assign wbm_ack_i = (readdatavalid & !waitrequest) | (write & !waitrequest);
|
|
|
`define MODULE wb3wb3_bridge
|
`define MODULE wb3wb3_bridge
|
`BASE`MODULE (
|
`BASE`MODULE wbwb3inst (
|
`undef MODULE
|
`undef MODULE
|
// wishbone slave side
|
// wishbone slave side
|
.wbs_dat_i(wbs_dat_i),
|
.wbs_dat_i(wbs_dat_i),
|
.wbs_adr_i(wbs_adr_i),
|
.wbs_adr_i(wbs_adr_i),
|
.wbs_sel_i(wbs_sel_i),
|
.wbs_sel_i(wbs_sel_i),
|
