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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Diff between revs 90 and 91

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Rev 90 Rev 91
Line 3711... Line 3711...
endmodule
endmodule
`endif
`endif
 
 
`ifdef RAM_BE
`ifdef RAM_BE
`define MODULE ram_be
`define MODULE ram_be
module `BASE`MODULE ( d, adr, be, re, we, q, clk);
module `BASE`MODULE ( d, adr, be, we, q, clk);
`undef MODULE
`undef MODULE
 
 
   parameter data_width = 32;
   parameter data_width = 32;
   parameter addr_width = 6;
   parameter addr_width = 6;
   parameter mem_size = 1<<addr_width;
   parameter mem_size = 1<<addr_width;
   input [(data_width-1):0]      d;
   input [(data_width-1):0]      d;
   input [(addr_width-1):0]       adr;
   input [(addr_width-1):0]       adr;
   input [(data_width/8)-1:0]    be;
   input [(data_width/8)-1:0]    be;
   input                         re;
 
   input                         we;
   input                         we;
   output reg [(data_width-1):0] q;
   output reg [(data_width-1):0] q;
   input                         clk;
   input                         clk;
 
 
 
 
Line 3755... Line 3754...
        if(be[3]) ram[adr][3] <= d[31:24];
        if(be[3]) ram[adr][3] <= d[31:24];
        if(be[2]) ram[adr][2] <= d[23:16];
        if(be[2]) ram[adr][2] <= d[23:16];
        if(be[1]) ram[adr][1] <= d[15:8];
        if(be[1]) ram[adr][1] <= d[15:8];
        if(be[0]) ram[adr][0] <= d[7:0];
        if(be[0]) ram[adr][0] <= d[7:0];
    end
    end
    if (re)
 
        q <= ram[adr];
        q <= ram[adr];
end
end
 
 
`else
`else
 
 
Line 3771... Line 3769...
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
   end
   end
   endgenerate
   endgenerate
 
 
   always @ (posedge clk)
   always @ (posedge clk)
    if (re)
 
      q <= ram[adr];
      q <= ram[adr];
 
 
`endif
`endif
 
 
   // Function to access RAM (for use by Verilator).
   // Function to access RAM (for use by Verilator).
Line 3921... Line 3918...
          ram[adr_b] <= d_b;
          ram[adr_b] <= d_b;
     end
     end
endmodule
endmodule
`endif
`endif
 
 
`ifdef DPRAM_MIXED_WIDTH_2R2W
 
`define MODULE dpram_mixed_width_2r2w
 
module `BASE`MODULE ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
 
`undef MODULE
 
   parameter data_width = 32;
 
   parameter addr_width = 8;
 
   parameter data_width_ratio = 2;
 
   parameter b_data_width = data_width * data_width_ratio;
 
   parameter b_addr_width = addr_width ;
 
endmodule
 
`endif
 
 
 
`ifdef DPRAM_BE_2R2W
`ifdef DPRAM_BE_2R2W
`define MODULE dpram_be_2r2w
`define MODULE dpram_be_2r2w
module `BASE`MODULE ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
module `BASE`MODULE ( d_a, q_a, adr_a, be_a, re_a, we_a, clk_a, d_b, q_b, adr_b, re_b, we_b, clk_b );
`undef MODULE
`undef MODULE
 
 
   parameter a_data_width = 32;
   parameter a_data_width = 32;
   parameter a_addr_width = 8;
   parameter a_addr_width = 8;
   parameter b_data_width = 64;
   parameter b_data_width = 32;
   parameter b_addr_width = 7;
   localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
   //parameter mem_size = (a_addr_width>b_addr_width) ? (1<<a_addr_width) : (1<<b_addr_width);
   parameter mem_size = (a_addr_width>b_addr_width) ? (1<<a_addr_width) : (1<<b_addr_width);
   parameter mem_size = 1024;
 
   input [(a_data_width-1):0]      d_a;
   input [(a_data_width-1):0]      d_a;
   input [(a_addr_width-1):0]     adr_a;
   input [(a_addr_width-1):0]     adr_a;
   input [(b_addr_width-1):0]     adr_b;
   input [(a_data_width/8-1):0]    be_a;
   input [(a_data_width/4-1):0]    be_a;
   input                           re_a;
   input                         we_a;
   input                         we_a;
   output [(b_data_width-1):0]    q_b;
 
   input [(b_data_width-1):0]     d_b;
 
   output reg [(a_data_width-1):0] q_a;
   output reg [(a_data_width-1):0] q_a;
   input [(b_data_width/4-1):0]    be_b;
   input [(b_data_width-1):0]       d_b;
   input                         we_b;
   input [(b_addr_width-1):0]       adr_b;
 
   input                           re_b,we_b;
 
   output [(b_data_width-1):0]      q_b;
   input                         clk_a, clk_b;
   input                         clk_a, clk_b;
   reg [(b_data_width-1):0]       q_b;
 
 
`ifdef SYSTEMVERILOG
 
// use a multi-dimensional packed array
 
//to model individual bytes within the word
 
 
generate
generate
if (a_data_width==32 & b_data_width==64) begin : inst32to64
if (a_data_width==32 & b_data_width==32) begin : dpram_3232
 
 
    wire [63:0] tmp;
   logic [3:0][7:0] ram [0:mem_size-1];
    `define MODULE dpram_2r2w
    reg [a_addr_width-1:0] rd_adr_a;
    `BASE`MODULE
    reg [b_addr_width-1:0] rd_adr_b;
    # (.data_width(8), .addr_width(b_addr_width-3))
 
    ram0 (
    always_ff@(posedge clk_a)
        .d_a(d_a[7:0]),
    begin
        .q_a(tmp[7:0]),
        if(we_a) begin
        .adr_a(adr_a[a_addr_width-3-1:0]),
            if(be_a[3]) ram[adr_a][3] <= d_a[31:24];
        .we_a(we_a & be_a[0] & !adr_a[0]),
            if(be_a[2]) ram[adr_a][2] <= d_a[23:16];
        .clk_a(clk_a),
            if(be_a[1]) ram[adr_a][1] <= d_a[15:8];
        .d_b(d_b[7:0]),
            if(be_a[0]) ram[adr_a][0] <= d_a[7:0];
        .q_b(q_b[7:0]),
 
        .adr_b(adr_b[b_addr_width-3-1:0]),
 
        .we_b(we_b),
 
        .clk_b(clk_b) );
 
    `BASE`MODULE
 
    # (.data_width(8), .addr_width(b_addr_width-3))
 
    ram1 (
 
        .d_a(d_a[7:0]),
 
        .q_a(tmp[7:0]),
 
        .adr_a(adr_a[a_addr_width-3-1:0]),
 
        .we_a(we_a),
 
        .clk_a(clk_a),
 
        .d_b(d_b[7:0]),
 
        .q_b(q_b[7:0]),
 
        .adr_b(adr_b[b_addr_width-3-1:0]),
 
        .we_b(we_b),
 
        .clk_b(clk_b) );
 
    `BASE`MODULE
 
    # (.data_width(8), .addr_width(b_addr_width-3))
 
    ram2 (
 
        .d_a(d_a[15:8]),
 
        .q_a(tmp[7:0]),
 
        .adr_a(adr_a[a_addr_width-3-1:0]),
 
        .we_a(we_a),
 
        .clk_a(clk_a),
 
        .d_b(d_b[7:0]),
 
        .q_b(q_b[7:0]),
 
        .adr_b(adr_b[b_addr_width-3-1:0]),
 
        .we_b(we_b),
 
        .clk_b(clk_b) );
 
    `BASE`MODULE
 
    # (.data_width(8), .addr_width(b_addr_width-3))
 
    ram3 (
 
        .d_a(d_a[15:8]),
 
        .q_a(tmp[7:0]),
 
        .adr_a(adr_a[a_addr_width-3-1:0]),
 
        .we_a(we_a),
 
        .clk_a(clk_a),
 
        .d_b(d_b[7:0]),
 
        .q_b(q_b[7:0]),
 
        .adr_b(adr_b[b_addr_width-3-1:0]),
 
        .we_b(we_b),
 
        .clk_b(clk_b) );
 
    `BASE`MODULE
 
    # (.data_width(8), .addr_width(b_addr_width-3))
 
    ram4 (
 
        .d_a(d_a[23:16]),
 
        .q_a(tmp[7:0]),
 
        .adr_a(adr_a[a_addr_width-3-1:0]),
 
        .we_a(we_a),
 
        .clk_a(clk_a),
 
        .d_b(d_b[7:0]),
 
        .q_b(q_b[7:0]),
 
        .adr_b(adr_b[b_addr_width-3-1:0]),
 
        .we_b(we_b),
 
        .clk_b(clk_b) );
 
    `BASE`MODULE
 
    # (.data_width(8), .addr_width(b_addr_width-3))
 
    ram5 (
 
        .d_a(d_a[23:16]),
 
        .q_a(tmp[7:0]),
 
        .adr_a(adr_a[a_addr_width-3-1:0]),
 
        .we_a(we_a),
 
        .clk_a(clk_a),
 
        .d_b(d_b[7:0]),
 
        .q_b(q_b[7:0]),
 
        .adr_b(adr_b[b_addr_width-3-1:0]),
 
        .we_b(we_b),
 
        .clk_b(clk_b) );
 
    `BASE`MODULE
 
    # (.data_width(8), .addr_width(b_addr_width-3))
 
    ram6 (
 
        .d_a(d_a[31:24]),
 
        .q_a(tmp[7:0]),
 
        .adr_a(adr_a[a_addr_width-3-1:0]),
 
        .we_a(we_a),
 
        .clk_a(clk_a),
 
        .d_b(d_b[7:0]),
 
        .q_b(q_b[7:0]),
 
        .adr_b(adr_b[b_addr_width-3-1:0]),
 
        .we_b(we_b),
 
        .clk_b(clk_b) );
 
    `BASE`MODULE
 
    # (.data_width(8), .addr_width(b_addr_width-3))
 
    ram7 (
 
        .d_a(d_a[31:24]),
 
        .q_a(tmp[7:0]),
 
        .adr_a(adr_a[a_addr_width-3-1:0]),
 
        .we_a(we_a),
 
        .clk_a(clk_a),
 
        .d_b(d_b[7:0]),
 
        .q_b(q_b[7:0]),
 
        .adr_b(adr_b[b_addr_width-3-1:0]),
 
        .we_b(we_b),
 
        .clk_b(clk_b) );
 
`undef MODULE
 
/*
 
   reg [7:0] ram0 [mem_size/8-1:0];
 
   wire [7:0] wea, web;
 
   assign wea = we_a & be_a[0];
 
   assign web = we_b & be_b[0];
 
   always @ (posedge clk_a)
 
    if (wea)
 
        ram0[adr_a] <= d_a[7:0];
 
    always @ (posedge clk_a)
 
        q_a[7:0] <= ram0[adr_a];
 
   always @ (posedge clk_a)
 
    if (web)
 
        ram0[adr_b] <= d_b[7:0];
 
    always @ (posedge clk_b)
 
        q_b[7:0] <= ram0[adr_b];
 
*/
 
end
end
endgenerate
    end
/*
 
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_rama
    always@(posedge clk_a or posedge rst)
      always @ (posedge clk_a)
    if (rst)
      if (we_a & be_a[i])
        rd_adr_a <= 0;
        ram[adr_a][(i+1)*8-1:i*8] <= d_a[(i+1)*8-1:i*8];
    else if (re_a)
   end
        rd_adr_a <= adr_a;
   endgenerate
 
 
    assign q_a = ram[rd_adr_a];
 
 
 
    always_ff@(posedge clk_b)
 
    if(we_b)
 
        ram[adr_b] <= d_b;
 
 
 
    always@(posedge clk_b or posedge rst)
 
    if (rst)
 
        rd_adr_b <= 0;
 
    else if (re_b)
 
        rd_adr_b <= adr_b;
 
 
   always @ (posedge clk_a)
    assign q_b = ram[rd_adr_b];
      q_a <= ram[adr_a];
 
 
 
   genvar i;
end
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ramb
 
      always @ (posedge clk_a)
 
      if (we_b & be_b[i])
 
        ram[adr_b][(i+1)*8-1:i*8] <= d_b[(i+1)*8-1:i*8];
 
   end
 
   endgenerate
   endgenerate
 
 
   always @ (posedge clk_b)
`else
      q_b <= ram[adr_b];
`endif
*/
 
/*
 
   always @ (posedge clk_a)
 
     begin
 
        q_a <= ram[adr_a];
 
        if (we_a)
 
             ram[adr_a] <= d_a;
 
     end
 
   always @ (posedge clk_b)
 
     begin
 
        q_b <= ram[adr_b];
 
        if (we_b)
 
          ram[adr_b] <= d_b;
 
     end
 
*/
 
endmodule
endmodule
`endif
`endif
 
 
 
`ifdef CAM
// Content addresable memory, CAM
// Content addresable memory, CAM
 
`endif
 
 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
// FIFO
// FIFO
`define MODULE fifo_1r1w_fill_level_sync
`define MODULE fifo_1r1w_fill_level_sync
module `BASE`MODULE (
module `BASE`MODULE (
Line 4685... Line 4554...
output ack_o;
output ack_o;
input clk, rst;
input clk, rst;
 
 
reg [adr_width-1:0] adr;
reg [adr_width-1:0] adr;
wire [max_burst_width-1:0] to_adr;
wire [max_burst_width-1:0] to_adr;
 
reg [max_burst_width-1:0] last_adr;
 
reg [1:0] last_cycle;
 
localparam idle = 2'b00;
 
localparam cyc  = 2'b01;
 
localparam ws   = 2'b10;
 
localparam eoc  = 2'b11;
 
 
 
always @ (posedge clk or posedge rst)
 
if (rst)
 
    last_adr <= {max_burst_width{1'b0}};
 
else
 
    if (stb_i)
 
        last_adr <=adr_o;
 
 
generate
generate
if (max_burst_width==0) begin : inst_0
if (max_burst_width==0) begin : inst_0
    reg ack_o;
    reg ack_o;
    assign adr_o = adr_i;
    assign adr_o = adr_i;
Line 4697... Line 4579...
        ack_o <= 1'b0;
        ack_o <= 1'b0;
    else
    else
        ack_o <= cyc_i & stb_i & !ack_o;
        ack_o <= cyc_i & stb_i & !ack_o;
end else begin
end else begin
 
 
    reg [1:0] last_cycle;
 
    localparam idle = 2'b00;
 
    localparam cyc  = 2'b01;
 
    localparam ws   = 2'b10;
 
    localparam eoc  = 2'b11;
 
    always @ (posedge clk or posedge rst)
    always @ (posedge clk or posedge rst)
    if (rst)
    if (rst)
        last_cycle <= idle;
        last_cycle <= idle;
    else
    else
        last_cycle <= (!cyc_i) ? idle :
        last_cycle <= (!cyc_i) ? idle :
                      (cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? eoc :
                      (cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? eoc :
                      (cyc_i & !stb_i) ? ws :
                      (cyc_i & !stb_i) ? ws :
                      cyc;
                      cyc;
    assign to_adr = (last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
    assign to_adr = (last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
    assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
    assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
 
                                        (!stb_i) ? last_adr :
                                        (last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] :
                                        (last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] :
                                        adr[max_burst_width-1:0];
                                        adr[max_burst_width-1:0];
    assign ack_o = (last_cycle==cyc | last_cycle==ws) & stb_i;
    assign ack_o = (last_cycle==cyc | last_cycle==ws) & stb_i;
end
end
endgenerate
endgenerate
Line 4753... Line 4631...
if (max_burst_width==4) begin : inst_4
if (max_burst_width==4) begin : inst_4
    always @ (posedge clk or posedge rst)
    always @ (posedge clk or posedge rst)
    if (rst)
    if (rst)
        adr <= 4'h0;
        adr <= 4'h0;
    else
    else
        if (cyc_i & stb_i)
        if (stb_i) // | (!stb_i & last_cycle!=ws)) // for !stb_i restart with adr_i +1, only inc once
            case (bte_i)
            case (bte_i)
            2'b01: adr[3:0] <= {to_adr[3:2],to_adr[1:0] + 2'd1};
            2'b01: adr[3:0] <= {to_adr[3:2],to_adr[1:0] + 2'd1};
            2'b10: adr[3:0] <= {to_adr[3],to_adr[2:0] + 3'd1};
            2'b10: adr[3:0] <= {to_adr[3],to_adr[2:0] + 3'd1};
            default: adr[3:0] <= to_adr + 4'd1;
            default: adr[3:0] <= to_adr + 4'd1;
            endcase
            endcase
Line 5465... Line 5343...
ram0(
ram0(
`undef MODULE
`undef MODULE
    .d(wbs_dat_i),
    .d(wbs_dat_i),
    .adr(adr),
    .adr(adr),
    .be(wbs_sel_i),
    .be(wbs_sel_i),
    .re(wbs_stb_i),
 
    .we(wbs_we_i & wbs_ack_o),
    .we(wbs_we_i & wbs_ack_o),
    .q(wbs_dat_o),
    .q(wbs_dat_o),
    .clk(wb_clk)
    .clk(wb_clk)
);
);
 
 

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