| Line 75... |
Line 75... |
`define WB_B3_RAM_BE
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`define WB_B3_RAM_BE
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`define WB_B4_RAM_BE
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`define WB_B4_RAM_BE
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`define WB_B4_ROM
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`define WB_B4_ROM
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`define WB_BOOT_ROM
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`define WB_BOOT_ROM
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`define WB_DPRAM
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`define WB_DPRAM
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`define WBB3_WBB4_CACHE
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|
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`define IO_DFF_OE
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`define IO_DFF_OE
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`define O_DFF
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`define O_DFF
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|
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`endif
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`endif
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| Line 156... |
Line 157... |
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
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`ifndef FIFO_2R2W_ASYNC_SIMPLEX
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`define FIFO_2R2W_ASYNC_SIMPLEX
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`define FIFO_2R2W_ASYNC_SIMPLEX
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`endif
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`endif
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`endif
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`endif
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|
|
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`ifdef WBB3_WBB4_CACHE
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`ifndef RAM
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`define RAM
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`endif
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`ifndef WB_ADR_INC
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`define WB_ADR_INC
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`endif
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`ifndef dpram_be_2r2w
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`define DPRAM_BE_2R2W
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`endif
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`endif
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|
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`ifdef MULTS18X18
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`ifdef MULTS18X18
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`ifndef MULTS
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`ifndef MULTS
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`define MULTS
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`define MULTS
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`endif
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`endif
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`endif
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`endif
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| Line 266... |
Line 279... |
`ifdef REG_FILE
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`ifdef REG_FILE
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`ifndef DPRAM_1R1W
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`ifndef DPRAM_1R1W
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`define DPRAM_1R1W
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`define DPRAM_1R1W
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`endif
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`endif
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`endif
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`endif
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// size to width
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`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Versatile library, clock and reset ////
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//// Versatile library, clock and reset ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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| Line 1181... |
Line 1197... |
`endif
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`endif
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|
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`ifdef TOGGLE2PULSE
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`ifdef TOGGLE2PULSE
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`define MODULE toggle2pulse;
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`define MODULE toggle2pulse;
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module `BASE`MODULE (d, pl, clk, rst);
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module `BASE`MODULE (d, pl, clk, rst);
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`undef MODULE
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input d;
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input d;
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output pl;
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output pl;
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input clk, rst;
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input clk, rst;
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reg dff;
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reg dff;
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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| Line 1212... |
Line 1229... |
endmodule
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endmodule
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`endif
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`endif
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|
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`ifdef CDC
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`ifdef CDC
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`define MODULE cdc
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`define MODULE cdc
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module `BASE`MODULE ( start_pl, take_it_pl, take_it_grant_pl, got_it_pl, clk_src, rst_src, clk_dst, rst_dst)
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module `BASE`MODULE ( start_pl, take_it_pl, take_it_grant_pl, got_it_pl, clk_src, rst_src, clk_dst, rst_dst);
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`undef MODULE
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`undef MODULE
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input start_pl;
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input start_pl;
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output take_it_pl;
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output take_it_pl;
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input take_it_grant_pl; // note: connect to take_it_pl to generate automatic ack
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input take_it_grant_pl; // note: connect to take_it_pl to generate automatic ack
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output got_it_pl;
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output got_it_pl;
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| Line 4753... |
Line 4770... |
if (stb_i)
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if (stb_i)
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last_adr <=adr_o[max_burst_width-1:0];
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last_adr <=adr_o[max_burst_width-1:0];
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|
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generate
|
generate
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if (max_burst_width==0) begin : inst_0
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if (max_burst_width==0) begin : inst_0
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|
|
reg ack_o;
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reg ack_o;
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assign adr_o = adr_i;
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assign adr_o = adr_i;
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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if (rst)
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if (rst)
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ack_o <= 1'b0;
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ack_o <= 1'b0;
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else
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else
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ack_o <= cyc_i & stb_i & !ack_o;
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ack_o <= cyc_i & stb_i & !ack_o;
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|
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end else begin
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end else begin
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|
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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if (rst)
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if (rst)
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last_cycle <= idle_or_eoc;
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last_cycle <= idle_or_eoc;
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| Line 4776... |
Line 4795... |
assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
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assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
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(!stb_i) ? last_adr :
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(!stb_i) ? last_adr :
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(last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] :
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(last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] :
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adr[max_burst_width-1:0];
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adr[max_burst_width-1:0];
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assign ack_o = (last_cycle==cyc_or_ws) & stb_i;
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assign ack_o = (last_cycle==cyc_or_ws) & stb_i;
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|
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end
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end
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endgenerate
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endgenerate
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|
|
generate
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generate
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if (max_burst_width==2) begin : inst_2
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if (max_burst_width==2) begin : inst_2
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| Line 5817... |
Line 5837... |
.clk_b(wbsb_clk) );
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.clk_b(wbsb_clk) );
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|
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endmodule
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endmodule
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`endif
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`endif
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|
|
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`ifdef WBB3_WBB4_CACHE
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`define MODULE wbb3_wbb4_cache
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module `BASE`MODULE (
|
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wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
|
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wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_dat_i, wbm_ack_i, wbm_stall_i, wbm_clk, wbm_rst
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);
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`undef MODULE
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|
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parameter dw_s = 32;
|
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parameter aw_s = 24;
|
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parameter dw_m = dw_s;
|
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parameter aw_m = dw_s * aw_s / dw_m;
|
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parameter max_burst_width = 4;
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|
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parameter async = 1; // wbs_clk != wbm_clk
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|
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parameter nr_of_ways = 1;
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parameter aw_offset = 4; // 4 => 16 words per cache line
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parameter aw_slot = 10;
|
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localparam aw_tag = aw_s - aw_tag_mem - aw_offset;
|
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parameter wbm_burst_size = 4; // valid options 4,8,16
|
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`define SIZE2WIDTH wbm_burst_size
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localparam wbm_burst_width `SIZE2WIDTH_EXPR
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`undef SIZE2WIDTH
|
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localparam nr_of_wbm_burst = ((1<<aw_offset)/wbm_burst_size) * dw_s / dw_m;
|
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`define SIZE2WIDTH nr_of_wbm_burst
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localparam nr_of_wbm_burst_width `SIZE2WIDTH_EXPR
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`undef SIZE2WIDTH
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input [dw_s-1:0] wbs_dat_i;
|
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input [aw_s-1:0] wbs_adr_i; // dont include a1,a0
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input [dw_s/8-1:0] wbs-sel_i;
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input [2:0] wbs_cti_i;
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input [1:0] wbs_bte_i;
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input wbs_we_i;
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output [dw_s-1:0] wbs_dat_o;
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output wbs_ack_o;
|
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input wbs_clk, wbs_rst;
|
|
|
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output [dw_m-1:0] wbm_dat_o;
|
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output [aw_m-1:0] wbm_adr_o;
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output [dw_m/8-1:0] wbm_sel_o;
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output [2:0] wbm_cti_o;
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output [1:0] wbm_bte_o;
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input [dw_m-1:0] wbm_dat_i;
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input wbm_ack_i;
|
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input wbm_stall_i;
|
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input wbm_clk, wbm_rst;
|
|
|
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wire dirty, valid;
|
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wire [aw_tag-1:0] tag;
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wire tag_mem_we;
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wire [aw_tag-1:0] wbs_adr_tag;
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wire [aw_slot-1:0] wbs_adr_slot;
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wire [aw_offset_1:0] wbs_adr_word;
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wire [aw-1:0] wbs_adr;
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|
|
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reg [1:0] state;
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localparam idle = 2'h0;
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localparam rdwr = 2'h1;
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|
localparam push = 2'h2;
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localparam pull = 2'h3;
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wire eoc;
|
|
|
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// cdc
|
|
wire done, mem_alert, mem_done;
|
|
|
|
assign {wbs_adr_tag, wbs_adr_slot, wbs_adr_word} = wbs_adr_i;
|
|
assign eoc = (wbs_cti_i==3'b000 | wbs_cti_i==3'b111) & wbs_ack_o;
|
|
|
|
`define MODULE ram
|
|
`BASE`MODULE
|
|
# ( .data_width(aw_tag), .addr_Width(aw_slot))
|
|
tag_mem ( .d(wbs_adr_slot), .adr(wbs_adr_tag), .we(done), .q(tag), .clk(wbs_clk));
|
|
`undef MODULE
|
|
assign valid = wbs_adr_tag == tag;
|
|
|
|
`define MODULE wb_adr_inc
|
|
`BASE`MODULE # ( .adr_width(aw_slot+aw_offset), .max_burst_width(max_burst_width)) adr_inc0 (
|
|
.cyc_i(wbs_cyc_i),
|
|
.stb_i(wbs_stb_i & (state==idle | (state==rw & valid))), // throttle depending on valid
|
|
.cti_i(wbs_cti_i),
|
|
.bte_i(wbs_bte_i),
|
|
.adr_i(wbs_adr_i),
|
|
.we_i (wbs_we_i),
|
|
.ack_o(wbs_ack_o),
|
|
.adr_o(wbs_adr),
|
|
.clk(wbsa_clk),
|
|
.rst(wbsa_rst));
|
|
`undef MODULE
|
|
|
|
`define MODULE dpram_be_2r2w
|
|
`BASE`MODULE
|
|
# ( .data_width(aw_tag), .addr_Width(aw_slot+aw_offset))
|
|
cache_mem ( .d_a(wbs_dat_i), .adr_a(wbs_adr), be_a(wbs_sel_i), .we_a(wbs_cyc_i & wbs_we_i & wbs_ack_o), .q_a(wbs_dat_o), .clk_a(wbs_clk),
|
|
.d_b(wbm_dat_i), .adr_b(wbm_adr), be_b(wbm_sel_o), .we_b(wbm_cyc_o & !wbm_we_o & wbs_ack_i), .q_b(wbm_dat_o), .clk_b(wbm_clk));
|
|
`undef MODULE
|
|
|
|
always @ (posedge wbs_clk or posedge wbs_rst)
|
|
if (wbs_rst)
|
|
case <= idle;
|
|
else
|
|
case (state)
|
|
idle:
|
|
if (wbs_cyc_i)
|
|
state <= rdwr;
|
|
rdwr:
|
|
if (wbs_we_i & valid & eoc)
|
|
state <= idle;
|
|
else if (wbs_we_i & !valid)
|
|
state <= pull;
|
|
else if (!wbs_we_i & valid & eoc)
|
|
state <= idle;
|
|
else if (!wbs_we_i & !valid & !dirty)
|
|
state <= pull;
|
|
else if (!wbs_we_i & !valid & dirty)
|
|
state <= push;
|
|
push:
|
|
if (done)
|
|
state <= rdwr;
|
|
pull:
|
|
if (done)
|
|
state <= rdwr;
|
|
default: state <= idle;
|
|
endcase
|
|
|
|
|
|
// cdc
|
|
generate
|
|
if (async==1) begin : cdc0
|
|
`define MODULE cdc
|
|
`BASE`MODULE cdc0 ( .start_pl(state==rdwr & !valid), .take_it_pl(mem_alert), .take_it_grant_pl(mem_done), .got_it_pl(done), .clk_src(wbs_clk), .rst_src(wbs_rst), .clk_dst(wbm_clk), .rst_dst(wbm_rst));
|
|
`undef MODULE
|
|
end
|
|
else begin : nocdc
|
|
assign mem_alert = state==rdwr & !valid;
|
|
assign done = mem_done;
|
|
end
|
|
endgenerate
|
|
|
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
|
if (rst)
|
|
wbm_burst_adr <= {aw_wbm_burst{1'b0}};
|
|
else
|
|
if (wbm_cyc_o & wbm_stb_o & !wbm_stall_i))
|
|
wbm_burst_adr <= wbm_burst_adr + (aw_wbm_burst)'d1
|
|
|
|
// FSM generating a number of burts 4 cycles
|
|
// actual number depends on data width ratio
|
|
// nr_of_wbm_burst
|
|
reg [wbm_burst_width-1:0] cnt0;
|
|
reg [nr_of_wbm_burst_width-1:0] cnt1;
|
|
|
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
|
if (wbm_rst)
|
|
{cnt1,cnt0} <= {nr_of_wbm_burst_width+wbm_burst_width{1'b0}};
|
|
else
|
|
if (wbm_cyc_o & wbm_stb_o & !wbm_stall_i)
|
|
{cnt1,cnt0} <= (nr_of_wbm_burst_width+wbm_burst_width)1'd1;
|
|
|
|
|
|
endmodule
|
|
`endif
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Arithmetic functions ////
|
//// Arithmetic functions ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
