| Line 2742... |
Line 2742... |
wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
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wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
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assign hit_o = hit;
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assign hit_o = hit;
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assign wb_dat_o = wb_dat & {32{wb_ack}};
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assign wb_dat_o = wb_dat & {32{wb_ack}};
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assign wb_ack_o = wb_ack;
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assign wb_ack_o = wb_ack;
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endmodule
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endmodule
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module vl_wb_dpram (
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// wishbone slave side a
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wbsa_dat_i, wbsa_adr_i, wbsa_sel_i, wbsa_cti_i, wbsa_bte_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o, wbsa_stall_o,
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wbsa_clk, wbsa_rst,
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// wishbone slave side b
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wbsb_dat_i, wbsb_adr_i, wbsb_sel_i, wbsb_cti_i, wbsb_bte_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o, wbsb_stall_o,
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wbsb_clk, wbsb_rst);
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parameter data_width_a = 32;
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parameter data_width_b = data_width_a;
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parameter addr_width_a = 8;
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localparam addr_width_b = data_width_a * addr_width_a / data_width_b;
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parameter mem_size = (addr_width_a>addr_width_b) ? (1<<addr_width_a) : (1<<addr_width_b);
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parameter max_burst_width_a = 4;
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parameter max_burst_width_b = max_burst_width_a;
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parameter mode = "B3";
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input [data_width_a-1:0] wbsa_dat_i;
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input [addr_width_a-1:0] wbsa_adr_i;
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input [data_width_a/8-1:0] wbsa_sel_i;
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input [2:0] wbsa_cti_i;
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input [1:0] wbsa_bte_i;
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input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
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output [data_width_a-1:0] wbsa_dat_o;
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output wbsa_ack_o;
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output wbsa_stall_o;
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input wbsa_clk, wbsa_rst;
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input [data_width_b-1:0] wbsb_dat_i;
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input [addr_width_b-1:0] wbsb_adr_i;
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input [data_width_b/8-1:0] wbsb_sel_i;
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input [2:0] wbsb_cti_i;
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input [1:0] wbsb_bte_i;
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input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
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output [data_width_b-1:0] wbsb_dat_o;
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output wbsb_ack_o;
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output wbsb_stall_o;
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input wbsb_clk, wbsb_rst;
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wire [addr_width_a-1:0] adr_a;
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wire [addr_width_b-1:0] adr_b;
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wire we_a, we_b;
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generate
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if (mode=="B3") begin : b3_inst
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vl_wb_adr_inc # ( .adr_width(addr_width_a), .max_burst_width(max_burst_width_a)) adr_inc0 (
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.cyc_i(wbsa_cyc_i),
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.stb_i(wbsa_stb_i),
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.cti_i(wbsa_cti_i),
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.bte_i(wbsa_bte_i),
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.adr_i(wbsa_adr_i),
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.we_i(wbsa_we_i),
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.ack_o(wbsa_ack_o),
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.adr_o(adr_a),
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.clk(wbsa_clk),
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.rst(wbsa_rst));
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assign we_a = wbsa_we_i & wbsa_ack_o;
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vl_wb_adr_inc # ( .adr_width(addr_width_b), .max_burst_width(max_burst_width_b)) adr_inc1 (
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.cyc_i(wbsb_cyc_i),
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.stb_i(wbsb_stb_i),
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.cti_i(wbsb_cti_i),
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.bte_i(wbsb_bte_i),
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.adr_i(wbsb_adr_i),
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.we_i(wbsb_we_i),
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.ack_o(wbsb_ack_o),
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.adr_o(adr_b),
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.clk(wbsb_clk),
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.rst(wbsb_rst));
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assign we_b = wbsb_we_i & wbsb_ack_o;
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end else if (mode=="B4") begin : b4_inst
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always @ (posedge wbsa_clk or posedge wbsa_rst)
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if (wbsa_rst)
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wbsa_ack_o <= 1'b0;
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else
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wbsa_ack_o <= wbsa_stb_i & wbsa_cyc_i;
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assign wbsa_stall_o = 1'b0;
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assign we_a = wbsa_we_i & wbsa_cyc_i & wbsa_stb_i;
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always @ (posedge wbsb_clk or posedge wbsb_rst)
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if (wbsb_rst)
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wbsb_ack_o <= 1'b0;
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else
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wbsb_ack_o <= wbsb_stb_i & wbsb_cyc_i;
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assign wbsb_stall_o = 1'b0;
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assign we_b = wbsb_we_i & wbsb_cyc_i & wbsb_stb_i;
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end
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endgenerate
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vl_dpram_be_2r2w # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size))
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ram_i (
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.d_a(wbsa_dat_i),
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.q_a(wbsa_dat_o),
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.adr_a(adr_a),
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.be_a(wbsa_sel_i),
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.we_a(we_a),
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.clk_a(wbsa_clk),
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.d_b(wbsb_dat_i),
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.q_b(wbsb_dat_o),
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.adr_b(adr_b),
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.be_b(wbsb_sel_i),
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.we_b(we_b),
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.clk_b(wbsb_clk) );
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endmodule
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module vl_wb_cache (
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module vl_wb_cache (
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wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, wbs_dat_o, wbs_ack_o, wbs_stall_o, wbs_clk, wbs_rst,
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wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, wbs_dat_o, wbs_ack_o, wbs_stall_o, wbs_clk, wbs_rst,
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wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o, wbm_dat_i, wbm_ack_i, wbm_stall_i, wbm_clk, wbm_rst
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wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o, wbm_dat_i, wbm_ack_i, wbm_stall_i, wbm_clk, wbm_rst
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);
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);
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parameter dw_s = 32;
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parameter dw_s = 32;
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