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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Diff between revs 110 and 111

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Rev 110 Rev 111
Line 1707... Line 1707...
end
end
endgenerate
endgenerate
generate
generate
if (a_data_width==32 & b_data_width==16) begin : dpram_3216
if (a_data_width==32 & b_data_width==16) begin : dpram_3216
logic [31:0] temp;
logic [31:0] temp;
vl_dpram_be_2r2w # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .init(memory_init), .memory_file(memory_file))
vl_dpram_be_2r2w # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file))
dpram6464 (
dpram6464 (
    .d_a(d_a),
    .d_a(d_a),
    .q_a(q_a),
    .q_a(q_a),
    .adr_a(adr_a),
    .adr_a(adr_a),
    .be_a(be_a),
    .be_a(be_a),
Line 1732... Line 1732...
end
end
endgenerate
endgenerate
generate
generate
if (a_data_width==32 & b_data_width==64) begin : dpram_3264
if (a_data_width==32 & b_data_width==64) begin : dpram_3264
logic [63:0] temp;
logic [63:0] temp;
vl_dpram_be_2r2w # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .init(memory_init), .memory_file(memory_file))
vl_dpram_be_2r2w # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file))
dpram6464 (
dpram6464 (
    .d_a({d_a,d_a}),
    .d_a({d_a,d_a}),
    .q_a(temp),
    .q_a(temp),
    .adr_a(adr_a[a_addr_width-1:1]),
    .adr_a(adr_a[a_addr_width-1:1]),
    .be_a({be_a,be_a} & {{4{adr_a[0]}},{4{!adr_a[0]}}}),
    .be_a({be_a,be_a} & {{4{adr_a[0]}},{4{!adr_a[0]}}}),

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