URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Diff between revs 140 and 141

Rev 140	Rev 141
Line 2955...	Line 2955...
`input clk_a, clk_b;`	`input clk_a, clk_b;`
`generate`	`generate`
`if (debug==1) begin : debug_we`	`if (debug==1) begin : debug_we`
`always @ (posedge clk_a)`	`always @ (posedge clk_a)`
`if (we_a)`	`if (we_a)`
`$display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);`	`$display ("Debug: Value %h written on port A at address %h : time %t", d_a, adr_a, $time);`
`always @ (posedge clk_b)`	`always @ (posedge clk_b)`
`if (we_b)`	`if (we_b)`
`$display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);`	`$display ("Debug: Value %h written on port B at address %h : time %t", d_b, adr_b, $time);`
`end`	`end`
`endgenerate`	`endgenerate`
`ifdef SYSTEMVERILOG	`ifdef SYSTEMVERILOG
`// use a multi-dimensional packed array`	`// use a multi-dimensional packed array`
`//to model individual bytes within the word`	`//to model individual bytes within the word`