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module vl_reg_file (
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module vl_reg_file (
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a1, a2, a3, wd3, we3, rd1, rd2, clk
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a1, a2, a3, wd3, we3, rd1, rd2, clk
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);
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);
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parameter data_width = 32;
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parameter data_width = 32;
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parameter addr_width = 5;
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parameter addr_width = 5;
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parameter debug = 0;
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input [addr_width-1:0] a1, a2, a3;
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input [addr_width-1:0] a1, a2, a3;
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input [data_width-1:0] wd3;
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input [data_width-1:0] wd3;
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input we3;
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input we3;
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output [data_width-1:0] rd1, rd2;
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output [data_width-1:0] rd1, rd2;
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input clk;
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input clk;
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generate
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if (debug==1) begin : debug_we
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always @ (posedge clk)
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if (we)
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$display ("Value %h written at register %h : time %t", d, adr, $time);
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end
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endgenerate
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reg [data_width-1:0] wd3_reg;
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reg [data_width-1:0] wd3_reg;
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reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
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reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
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reg we3_reg;
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reg we3_reg;
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reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
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reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
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reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
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reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
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