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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Diff between revs 29 and 30

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Rev 29 Rev 30
Line 787... Line 787...
   output reg level2;
   output reg level2;
   input rst;
   input rst;
   input clk;
   input clk;
   parameter clear_value = 0;
   parameter clear_value = 0;
   parameter set_value = 1;
   parameter set_value = 1;
   parameter wrap_value = 7;
   parameter wrap_value = 15;
   parameter level1_value = 15;
   parameter level1_value = 8;
 
   parameter level2_value = 15;
   wire rew;
   wire rew;
   assign rew=1'b0;
   assign rew=1'b0;
   reg  [length:1] qi;
   reg  [length:1] qi;
   wire [length:1] q_next;
   wire [length:1] q_next;
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};

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