| Line 1120... |
Line 1120... |
end
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end
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endmodule
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endmodule
|
module vl_ram_be ( d, adr, be, we, q, clk);
|
module vl_ram_be ( d, adr, be, we, q, clk);
|
parameter data_width = 32;
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parameter data_width = 32;
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parameter addr_width = 8;
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parameter addr_width = 8;
|
|
parameter mem_size = 256;
|
input [(data_width-1):0] d;
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input [(data_width-1):0] d;
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input [(addr_width-1):0] adr;
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input [(addr_width-1):0] adr;
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input [(addr_width/4)-1:0] be;
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input [(addr_width/4)-1:0] be;
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input we;
|
input we;
|
output reg [(data_width-1):0] q;
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output reg [(data_width-1):0] q;
|
input clk;
|
input clk;
|
`ifdef SYSTEMVERILOG
|
`ifdef SYSTEMVERILOG
|
logic [data_width/8-1:0][7:0] ram[0:1<<(addr_width-2)-1];// # words = 1 << address width
|
logic [data_width/8-1:0][7:0] ram[0:mem_size-1];// # words = 1 << address width
|
`else
|
`else
|
reg [data_width-1:0] ram [(1<<addr_width)-1:0];
|
reg [data_width-1:0] ram [mem_size-1:0];
|
`endif
|
`endif
|
parameter memory_init = 0;
|
parameter memory_init = 0;
|
parameter memory_file = "vl_ram.vmem";
|
parameter memory_file = "vl_ram.vmem";
|
generate if (memory_init) begin : init_mem
|
generate if (memory_init) begin : init_mem
|
initial
|
initial
|
| Line 2051... |
Line 2052... |
module vl_wb_b3_ram_be (
|
module vl_wb_b3_ram_be (
|
wb_dat_i, wb_adr_i, wb_cti_i, wb_bte_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
|
wb_dat_i, wb_adr_i, wb_cti_i, wb_bte_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
|
wb_dat_o, wb_ack_o, wb_clk, wb_rst);
|
wb_dat_o, wb_ack_o, wb_clk, wb_rst);
|
parameter nr_of_ports = 3;
|
parameter nr_of_ports = 3;
|
parameter wb_arbiter_type = 1;
|
parameter wb_arbiter_type = 1;
|
parameter adr_size = 26;
|
parameter adr_size = 16;
|
parameter adr_lo = 2;
|
parameter adr_lo = 2;
|
|
parameter mem_size = 1<<16;
|
parameter dat_size = 32;
|
parameter dat_size = 32;
|
parameter memory_init = 1;
|
parameter memory_init = 1;
|
parameter memory_file = "vl_ram.vmem";
|
parameter memory_file = "vl_ram.vmem";
|
localparam aw = (adr_size - adr_lo) * nr_of_ports;
|
localparam aw = (adr_size - adr_lo) * nr_of_ports;
|
localparam dw = dat_size * nr_of_ports;
|
localparam dw = dat_size * nr_of_ports;
|
| Line 2128... |
Line 2130... |
end
|
end
|
endgenerate
|
endgenerate
|
vl_ram_be # (
|
vl_ram_be # (
|
.data_width(dat_size),
|
.data_width(dat_size),
|
.addr_width(adr_size),
|
.addr_width(adr_size),
|
.memory_init(1),
|
.memory_init(memory_init),
|
.memory_file("memory_file"))
|
.memory_file(memory_file))
|
ram0(
|
ram0(
|
.d(wbs_dat_i),
|
.d(wbs_dat_i),
|
.adr(wbs_adr_i[adr_size-1:2]),
|
.adr(wbs_adr_i[adr_size-1:2]),
|
.be(wbs_sel_i),
|
.be(wbs_sel_i),
|
.we(wbs_we_i),
|
.we(wbs_we_i),
|
