URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Diff between revs 71 and 72

Rev 71	Rev 72
Line 1119...	Line 1119...
`q <= ram[adr];`	`q <= ram[adr];`
`end`	`end`
`endmodule`	`endmodule`
`module vl_ram_be ( d, adr, be, we, q, clk);`	`module vl_ram_be ( d, adr, be, we, q, clk);`
`parameter data_width = 32;`	`parameter data_width = 32;`
`parameter addr_width = 8;`	`parameter addr_width = 6;`
`parameter mem_size = 256;`	`parameter mem_size = 256;`
`input [(data_width-1):0] d;`	`input [(data_width-1):0] d;`
`input [(addr_width-1):0] adr;`	`input [(addr_width-1):0] adr;`
`input [(addr_width/4)-1:0] be;`	`input [(addr_width/4)-1:0] be;`
`input we;`	`input we;`
Line 2074...	Line 2074...
`input wb_clk, wb_rst;`	`input wb_clk, wb_rst;`
`wire [sw-1:0] cke;`	`wire [sw-1:0] cke;`
`reg wbs_ack_o;`	`reg wbs_ack_o;`
`vl_ram_be # (`	`vl_ram_be # (`
`.data_width(dat_size),`	`.data_width(dat_size),`
`.addr_width(adr_size),`	`.addr_width(adr_size-2),`
`.mem_size(mem_size),`	`.mem_size(mem_size),`
`.memory_init(memory_init),`	`.memory_init(memory_init),`
`.memory_file(memory_file))`	`.memory_file(memory_file))`
`ram0(`	`ram0(`
`.d(wbs_dat_i),`	`.d(wbs_dat_i),`