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Line 1930... |
//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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// async wb3 - wb3 bridge
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// async wb3 - wb3 bridge
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`timescale 1ns/1ns
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`timescale 1ns/1ns
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module vl_wb_adr_inc ( cyc_i, stb_i, cti_i, bte_i, adr_i, ack_o, adr_o, clk, rst);
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parameter adr_width = 10;
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parameter max_burst_width = 4;
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input cyc_i, stb_i;
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input [2:0] cti_i;
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input [1:0] bte_i;
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input [adr_width-1:0] adr_i;
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output [adr_width-1:0] adr_o;
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output ack_o;
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input clk, rst;
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reg [adr_width-1:0] adr;
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generate
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if (max_burst_width==0) begin : inst_0
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reg ack_o;
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assign adr_o = adr_i;
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always @ (posedge clk or posedge rst)
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if (rst)
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ack_o <= 1'b0;
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else
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ack_o <= cyc_i & stb_i & !ack_o;
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end else begin
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wire [max_burst_width-1:0] to_adr;
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reg [1:0] last_cycle;
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localparam idle = 2'b00;
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localparam cyc = 2'b01;
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localparam ws = 2'b10;
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localparam eoc = 2'b11;
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always @ (posedge clk or posedge rst)
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if (rst)
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last_cycle <= idle;
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else
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last_cycle <= (!cyc_i) ? idle :
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(cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? eoc :
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(cyc_i & !stb_i) ? ws :
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cyc;
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assign to_adr = (last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
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assign adr_o[max_burst_width-1:0] = (last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
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assign ack_o = last_cycle == cyc;
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end
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endgenerate
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generate
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if (max_burst_width==2) begin : inst_2
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always @ (posedge clk or posedge rst)
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if (rst)
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adr <= 2'h0;
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else
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if (cyc_i & stb_i)
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adr[1:0] <= to_adr[1:0] + 2'd1;
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else
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adr <= to_adr[1:0];
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end
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endgenerate
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generate
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if (max_burst_width==3) begin : inst_3
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always @ (posedge clk or posedge rst)
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if (rst)
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adr <= 3'h0;
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else
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if (cyc_i & stb_i)
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case (bte_i)
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2'b01: adr[2:0] <= {to_adr[2],to_adr[1:0] + 2'd1};
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default: adr[3:0] <= to_adr[2:0] + 3'd1;
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endcase
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else
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adr <= to_adr[2:0];
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end
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endgenerate
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generate
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if (max_burst_width==4) begin : inst_4
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always @ (posedge clk or posedge rst)
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if (rst)
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adr <= 4'h0;
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else
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if (cyc_i & stb_i)
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case (bte_i)
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2'b01: adr[3:0] <= {to_adr[3:2],to_adr[1:0] + 2'd1};
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2'b10: adr[3:0] <= {to_adr[3],to_adr[2:0] + 3'd1};
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default: adr[3:0] <= to_adr + 4'd1;
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endcase
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else
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adr <= to_adr[3:0];
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end
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endgenerate
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generate
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if (adr_width > max_burst_width) begin : pass_through
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assign adr_o[adr_width-1:max_burst_width] = adr_i[adr_width-1:max_burst_width];
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end
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endgenerate
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endmodule
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// async wb3 - wb3 bridge
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`timescale 1ns/1ns
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module vl_wb3wb3_bridge (
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module vl_wb3wb3_bridge (
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// wishbone slave side
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// wishbone slave side
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wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
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wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
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// wishbone master side
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// wishbone master side
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wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
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wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
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Line 2216... |
input [31:0] wbs_dat_i;
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input [31:0] wbs_dat_i;
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input [31:2] wbs_adr_i;
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input [31:2] wbs_adr_i;
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input [3:0] wbs_sel_i;
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input [3:0] wbs_sel_i;
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input [1:0] wbs_bte_i;
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input [1:0] wbs_bte_i;
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input [2:0] wbs_cti_i;
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input [2:0] wbs_cti_i;
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input wbs_we_i, wbs_cyc_i, wbs_stb_i;
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input wbs_we_i;
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input wbs_cyc_i;
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input wbs_stb_i;
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output [31:0] wbs_dat_o;
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output [31:0] wbs_dat_o;
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output wbs_ack_o;
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output wbs_ack_o;
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input wbs_clk, wbs_rst;
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input wbs_clk, wbs_rst;
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input [31:0] readdata;
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input [31:0] readdata;
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output [31:0] writedata;
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output [31:0] writedata;
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Line 2538... |
wbs_dat_o, wbs_ack_o, wb_clk, wb_rst);
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wbs_dat_o, wbs_ack_o, wb_clk, wb_rst);
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parameter adr_size = 16;
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parameter adr_size = 16;
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parameter adr_lo = 2;
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parameter adr_lo = 2;
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parameter mem_size = 1<<16;
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parameter mem_size = 1<<16;
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parameter dat_size = 32;
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parameter dat_size = 32;
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parameter max_burst_width = 4;
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parameter memory_init = 1;
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parameter memory_init = 1;
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parameter memory_file = "vl_ram.vmem";
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parameter memory_file = "vl_ram.vmem";
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localparam aw = (adr_size - adr_lo);
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localparam aw = (adr_size - adr_lo);
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localparam dw = dat_size;
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localparam dw = dat_size;
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localparam sw = dat_size/8;
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localparam sw = dat_size/8;
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Line 2555... |
input [sw-1:0] wbs_sel_i;
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input [sw-1:0] wbs_sel_i;
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input wbs_we_i, wbs_stb_i, wbs_cyc_i;
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input wbs_we_i, wbs_stb_i, wbs_cyc_i;
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output [dw-1:0] wbs_dat_o;
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output [dw-1:0] wbs_dat_o;
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output wbs_ack_o;
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output wbs_ack_o;
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input wb_clk, wb_rst;
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input wb_clk, wb_rst;
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wire [sw-1:0] cke;
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reg wbs_ack_o;
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reg wbs_ack_o;
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wire [aw-1:0] adr;
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vl_ram_be # (
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vl_ram_be # (
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.data_width(dat_size),
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.data_width(dat_size),
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.addr_width(adr_size-2),
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.addr_width(aw),
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.mem_size(mem_size),
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.mem_size(mem_size),
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.memory_init(memory_init),
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.memory_init(memory_init),
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.memory_file(memory_file))
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.memory_file(memory_file))
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ram0(
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ram0(
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.d(wbs_dat_i),
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.d(wbs_dat_i),
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.adr(wbs_adr_i[adr_size-1:2]),
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.adr(adr),
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.be(wbs_sel_i),
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.be(wbs_sel_i),
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.we(wbs_we_i),
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.we(wbs_we_i),
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.q(wbs_dat_o),
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.q(wbs_dat_o),
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.clk(wb_clk)
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.clk(wb_clk)
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);
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);
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always @ (posedge wb_clk or posedge wb_rst)
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vl_wb_adr_inc # ( .adr_width(aw), .max_burst_width(max_burst_width)) adr_inc0 (
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if (wb_rst)
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.cyc_i(wbs_cyc_i),
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wbs_ack_o <= 1'b0;
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.stb_i(wbs_stb_i),
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else
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.cti_i(wbs_cti_i),
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if (wbs_cti_i==3'b000 | wbs_cti_i==3'b111)
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.bte_i(wbs_bte_i),
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wbs_ack_o <= wbs_stb_i & wbs_cyc_i & !wbs_ack_o;
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.adr_i(wbs_adr_i),
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else
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.ack_o(wbs_ack_o),
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wbs_ack_o <= wbs_stb_i & wbs_cyc_i;
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.adr_o(adr),
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.clk(wb_clk),
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.rst(wb_rst));
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endmodule
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endmodule
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// WB RAM with byte enable
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// WB RAM with byte enable
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module vl_wb_b4_ram_be (
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module vl_wb_b4_ram_be (
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wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
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wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
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wb_dat_o, wb_stall_o, wb_ack_o, wb_clk, wb_rst);
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wb_dat_o, wb_stall_o, wb_ack_o, wb_clk, wb_rst);
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