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https://opencores.org/ocsvn/versatile_library/versatile_library/trunk
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| Rev 110 |
Rev 111 |
| Line 1814... |
Line 1814... |
end
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end
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endgenerate
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endgenerate
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generate
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generate
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if (a_data_width==32 & b_data_width==16) begin : dpram_3216
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if (a_data_width==32 & b_data_width==16) begin : dpram_3216
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logic [31:0] temp;
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logic [31:0] temp;
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vl_dpram_be_2r2w # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .init(memory_init), .memory_file(memory_file))
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vl_dpram_be_2r2w # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file))
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dpram6464 (
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dpram6464 (
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.d_a(d_a),
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.d_a(d_a),
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.q_a(q_a),
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.q_a(q_a),
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.adr_a(adr_a),
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.adr_a(adr_a),
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.be_a(be_a),
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.be_a(be_a),
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| Line 1839... |
Line 1839... |
end
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end
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endgenerate
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endgenerate
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generate
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generate
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if (a_data_width==32 & b_data_width==64) begin : dpram_3264
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if (a_data_width==32 & b_data_width==64) begin : dpram_3264
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logic [63:0] temp;
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logic [63:0] temp;
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vl_dpram_be_2r2w # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .init(memory_init), .memory_file(memory_file))
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vl_dpram_be_2r2w # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file))
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dpram6464 (
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dpram6464 (
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.d_a({d_a,d_a}),
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.d_a({d_a,d_a}),
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.q_a(temp),
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.q_a(temp),
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.adr_a(adr_a[a_addr_width-1:1]),
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.adr_a(adr_a[a_addr_width-1:1]),
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.be_a({be_a,be_a} & {{4{adr_a[0]}},{4{!adr_a[0]}}}),
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.be_a({be_a,be_a} & {{4{adr_a[0]}},{4{!adr_a[0]}}}),
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