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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Diff between revs 14 and 15

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Rev 14 Rev 15
Line 278... Line 278...
input d, le;
input d, le;
output q;
output q;
input clk;
input clk;
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
endmodule
endmodule
 
module delay ( d, q, clk, rst);
 
parameter depth = 10;
 
input d;
 
output q;
 
input clk, rst;
 
reg [1:depth] dffs;
 
always @ (posedge clk or posedge rst)
 
if (rst)
 
    dffs <= {depth{1'b0}};
 
else
 
    dffs <= {d,dffs[1:depth-1]};
 
assign q = dffs[depth];
 
endmodule
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////  Versatile counter                                           ////
////  Versatile counter                                           ////
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////  Description                                                 ////
////  Description                                                 ////

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