| Line 40... |
Line 40... |
//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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// Global buffer
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// Global buffer
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// usage:
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// usage:
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// use to enable global buffers for high fan out signals such as clock and reset
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// use to enable global buffers for high fan out signals such as clock and reset
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altera
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//altera
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// ALTERA
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// ALTERA
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//ACTEL
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//ACTEL
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// sync reset
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// sync reset
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// input active lo async reset, normally from external reset generator and/or switch
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// input active lo async reset, normally from external reset generator and/or switch
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// output active high global reset sync with two DFFs
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// output active high global reset sync with two DFFs
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| Line 379... |
Line 379... |
parameter width = 32;
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parameter width = 32;
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parameter nr_of_ports = 4;
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parameter nr_of_ports = 4;
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input [width-1:0] a3, a2, a1, a0;
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input [width-1:0] a3, a2, a1, a0;
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input [nr_of_ports-1:0] sel;
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input [nr_of_ports-1:0] sel;
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output reg [width-1:0] dout;
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output reg [width-1:0] dout;
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reg [width-1:0] tmp [nr_of_ports-1:0];
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wire [width-1:0] tmp [nr_of_ports-1:0];
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integer i;
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integer i;
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// and
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// and
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assign tmp[0] = {width{sel[0]}} & a0;
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assign tmp[0] = {width{sel[0]}} & a0;
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assign tmp[1] = {width{sel[1]}} & a1;
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assign tmp[1] = {width{sel[1]}} & a1;
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assign tmp[2] = {width{sel[2]}} & a2;
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assign tmp[2] = {width{sel[2]}} & a2;
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| Line 395... |
Line 395... |
parameter width = 32;
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parameter width = 32;
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parameter nr_of_ports = 5;
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parameter nr_of_ports = 5;
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input [width-1:0] a4, a3, a2, a1, a0;
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input [width-1:0] a4, a3, a2, a1, a0;
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input [nr_of_ports-1:0] sel;
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input [nr_of_ports-1:0] sel;
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output reg [width-1:0] dout;
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output reg [width-1:0] dout;
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reg [width-1:0] tmp [nr_of_ports-1:0];
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wire [width-1:0] tmp [nr_of_ports-1:0];
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integer i;
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integer i;
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// and
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// and
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assign tmp[0] = {width{sel[0]}} & a0;
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assign tmp[0] = {width{sel[0]}} & a0;
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assign tmp[1] = {width{sel[1]}} & a1;
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assign tmp[1] = {width{sel[1]}} & a1;
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assign tmp[2] = {width{sel[2]}} & a2;
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assign tmp[2] = {width{sel[2]}} & a2;
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| Line 412... |
Line 412... |
parameter width = 32;
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parameter width = 32;
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parameter nr_of_ports = 6;
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parameter nr_of_ports = 6;
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input [width-1:0] a5, a4, a3, a2, a1, a0;
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input [width-1:0] a5, a4, a3, a2, a1, a0;
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input [nr_of_ports-1:0] sel;
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input [nr_of_ports-1:0] sel;
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output reg [width-1:0] dout;
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output reg [width-1:0] dout;
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reg [width-1:0] tmp [nr_of_ports-1:0];
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wire [width-1:0] tmp [nr_of_ports-1:0];
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integer i;
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integer i;
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// and
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// and
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assign tmp[0] = {width{sel[0]}} & a0;
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assign tmp[0] = {width{sel[0]}} & a0;
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assign tmp[1] = {width{sel[1]}} & a1;
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assign tmp[1] = {width{sel[1]}} & a1;
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assign tmp[2] = {width{sel[2]}} & a2;
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assign tmp[2] = {width{sel[2]}} & a2;
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| Line 1698... |
Line 1698... |
input rd;
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input rd;
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output fifo_empty;
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output fifo_empty;
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input rd_clk;
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input rd_clk;
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input rd_rst;
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input rd_rst;
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wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
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wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
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vl_fifo_1r1w_async (
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/*
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d, wr, fifo_full, wr_clk, wr_rst,
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vl_fifo_1r1w_async (
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q, rd, fifo_empty, rd_clk, rd_rst
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d, wr, fifo_full, wr_clk, wr_rst,
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);
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q, rd, fifo_empty, rd_clk, rd_rst
|
|
);
|
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*/
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vl_cnt_gray_ce_bin
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vl_cnt_gray_ce_bin
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# ( .length(addr_width))
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# ( .length(addr_width))
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fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
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fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
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vl_cnt_gray_ce_bin
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vl_cnt_gray_ce_bin
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# (.length(addr_width))
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# (.length(addr_width))
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