//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Versatile library, clock and reset ////
|
//// Versatile library, clock and reset ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
//// Logic related to clock and reset ////
|
//// Logic related to clock and reset ////
|
//// ////
|
//// ////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
//// - add more different registers ////
|
//// - add more different registers ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// ORSoC AB ////
|
//// ORSoC AB ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
// Global buffer
|
// Global buffer
|
// usage:
|
// usage:
|
// use to enable global buffers for high fan out signals such as clock and reset
|
// use to enable global buffers for high fan out signals such as clock and reset
|
altera
|
//altera
|
// ALTERA
|
// ALTERA
|
//ACTEL
|
//ACTEL
|
// sync reset
|
// sync reset
|
// input active lo async reset, normally from external reset generator and/or switch
|
// input active lo async reset, normally from external reset generator and/or switch
|
// output active high global reset sync with two DFFs
|
// output active high global reset sync with two DFFs
|
`timescale 1 ns/100 ps
|
`timescale 1 ns/100 ps
|
module vl_sync_rst ( rst_n_i, rst_o, clk);
|
module vl_sync_rst ( rst_n_i, rst_o, clk);
|
input rst_n_i, clk;
|
input rst_n_i, clk;
|
output rst_o;
|
output rst_o;
|
reg [1:0] tmp;
|
reg [1:0] tmp;
|
always @ (posedge clk or negedge rst_n_i)
|
always @ (posedge clk or negedge rst_n_i)
|
if (!rst_n_i)
|
if (!rst_n_i)
|
tmp <= 2'b11;
|
tmp <= 2'b11;
|
else
|
else
|
tmp <= {1'b0,tmp[0]};
|
tmp <= {1'b0,tmp[0]};
|
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
|
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
|
endmodule
|
endmodule
|
// vl_pll
|
// vl_pll
|
//altera
|
//altera
|
//actel
|
//actel
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Versatile library, registers ////
|
//// Versatile library, registers ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
//// Different type of registers ////
|
//// Different type of registers ////
|
//// ////
|
//// ////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
//// - add more different registers ////
|
//// - add more different registers ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// ORSoC AB ////
|
//// ORSoC AB ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
module vl_dff ( d, q, clk, rst);
|
module vl_dff ( d, q, clk, rst);
|
parameter width = 1;
|
parameter width = 1;
|
parameter reset_value = 0;
|
parameter reset_value = 0;
|
input [width-1:0] d;
|
input [width-1:0] d;
|
input clk, rst;
|
input clk, rst;
|
output reg [width-1:0] q;
|
output reg [width-1:0] q;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
q <= reset_value;
|
q <= reset_value;
|
else
|
else
|
q <= d;
|
q <= d;
|
endmodule
|
endmodule
|
module vl_dff_array ( d, q, clk, rst);
|
module vl_dff_array ( d, q, clk, rst);
|
parameter width = 1;
|
parameter width = 1;
|
parameter depth = 2;
|
parameter depth = 2;
|
parameter reset_value = 1'b0;
|
parameter reset_value = 1'b0;
|
input [width-1:0] d;
|
input [width-1:0] d;
|
input clk, rst;
|
input clk, rst;
|
output [width-1:0] q;
|
output [width-1:0] q;
|
reg [0:depth-1] q_tmp [width-1:0];
|
reg [0:depth-1] q_tmp [width-1:0];
|
integer i;
|
integer i;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst) begin
|
if (rst) begin
|
for (i=0;i<depth;i=i+1)
|
for (i=0;i<depth;i=i+1)
|
q_tmp[i] <= {width{reset_value}};
|
q_tmp[i] <= {width{reset_value}};
|
end else begin
|
end else begin
|
q_tmp[0] <= d;
|
q_tmp[0] <= d;
|
for (i=1;i<depth;i=i+1)
|
for (i=1;i<depth;i=i+1)
|
q_tmp[i] <= q_tmp[i-1];
|
q_tmp[i] <= q_tmp[i-1];
|
end
|
end
|
assign q = q_tmp[depth-1];
|
assign q = q_tmp[depth-1];
|
endmodule
|
endmodule
|
module vl_dff_ce ( d, ce, q, clk, rst);
|
module vl_dff_ce ( d, ce, q, clk, rst);
|
parameter width = 1;
|
parameter width = 1;
|
parameter reset_value = 0;
|
parameter reset_value = 0;
|
input [width-1:0] d;
|
input [width-1:0] d;
|
input ce, clk, rst;
|
input ce, clk, rst;
|
output reg [width-1:0] q;
|
output reg [width-1:0] q;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
q <= reset_value;
|
q <= reset_value;
|
else
|
else
|
if (ce)
|
if (ce)
|
q <= d;
|
q <= d;
|
endmodule
|
endmodule
|
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
|
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
|
parameter width = 1;
|
parameter width = 1;
|
parameter reset_value = 0;
|
parameter reset_value = 0;
|
input [width-1:0] d;
|
input [width-1:0] d;
|
input ce, clear, clk, rst;
|
input ce, clear, clk, rst;
|
output reg [width-1:0] q;
|
output reg [width-1:0] q;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
q <= reset_value;
|
q <= reset_value;
|
else
|
else
|
if (ce)
|
if (ce)
|
if (clear)
|
if (clear)
|
q <= {width{1'b0}};
|
q <= {width{1'b0}};
|
else
|
else
|
q <= d;
|
q <= d;
|
endmodule
|
endmodule
|
// megafunction wizard: %LPM_FF%
|
// megafunction wizard: %LPM_FF%
|
// GENERATION: STANDARD
|
// GENERATION: STANDARD
|
// VERSION: WM1.0
|
// VERSION: WM1.0
|
// MODULE: lpm_ff
|
// MODULE: lpm_ff
|
// ============================================================
|
// ============================================================
|
// File Name: dff_sr.v
|
// File Name: dff_sr.v
|
// Megafunction Name(s):
|
// Megafunction Name(s):
|
// lpm_ff
|
// lpm_ff
|
//
|
//
|
// Simulation Library Files(s):
|
// Simulation Library Files(s):
|
// lpm
|
// lpm
|
// ============================================================
|
// ============================================================
|
// ************************************************************
|
// ************************************************************
|
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
//
|
//
|
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
|
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
|
// ************************************************************
|
// ************************************************************
|
//Copyright (C) 1991-2010 Altera Corporation
|
//Copyright (C) 1991-2010 Altera Corporation
|
//Your use of Altera Corporation's design tools, logic functions
|
//Your use of Altera Corporation's design tools, logic functions
|
//and other software and tools, and its AMPP partner logic
|
//and other software and tools, and its AMPP partner logic
|
//functions, and any output files from any of the foregoing
|
//functions, and any output files from any of the foregoing
|
//(including device programming or simulation files), and any
|
//(including device programming or simulation files), and any
|
//associated documentation or information are expressly subject
|
//associated documentation or information are expressly subject
|
//to the terms and conditions of the Altera Program License
|
//to the terms and conditions of the Altera Program License
|
//Subscription Agreement, Altera MegaCore Function License
|
//Subscription Agreement, Altera MegaCore Function License
|
//Agreement, or other applicable license agreement, including,
|
//Agreement, or other applicable license agreement, including,
|
//without limitation, that your use is for the sole purpose of
|
//without limitation, that your use is for the sole purpose of
|
//programming logic devices manufactured by Altera and sold by
|
//programming logic devices manufactured by Altera and sold by
|
//Altera or its authorized distributors. Please refer to the
|
//Altera or its authorized distributors. Please refer to the
|
//applicable agreement for further details.
|
//applicable agreement for further details.
|
// synopsys translate_off
|
// synopsys translate_off
|
`timescale 1 ps / 1 ps
|
`timescale 1 ps / 1 ps
|
// synopsys translate_on
|
// synopsys translate_on
|
module vl_dff_sr (
|
module vl_dff_sr (
|
aclr,
|
aclr,
|
aset,
|
aset,
|
clock,
|
clock,
|
data,
|
data,
|
q);
|
q);
|
input aclr;
|
input aclr;
|
input aset;
|
input aset;
|
input clock;
|
input clock;
|
input data;
|
input data;
|
output q;
|
output q;
|
wire [0:0] sub_wire0;
|
wire [0:0] sub_wire0;
|
wire [0:0] sub_wire1 = sub_wire0[0:0];
|
wire [0:0] sub_wire1 = sub_wire0[0:0];
|
wire q = sub_wire1;
|
wire q = sub_wire1;
|
wire sub_wire2 = data;
|
wire sub_wire2 = data;
|
wire sub_wire3 = sub_wire2;
|
wire sub_wire3 = sub_wire2;
|
lpm_ff lpm_ff_component (
|
lpm_ff lpm_ff_component (
|
.aclr (aclr),
|
.aclr (aclr),
|
.clock (clock),
|
.clock (clock),
|
.data (sub_wire3),
|
.data (sub_wire3),
|
.aset (aset),
|
.aset (aset),
|
.q (sub_wire0)
|
.q (sub_wire0)
|
// synopsys translate_off
|
// synopsys translate_off
|
,
|
,
|
.aload (),
|
.aload (),
|
.enable (),
|
.enable (),
|
.sclr (),
|
.sclr (),
|
.sload (),
|
.sload (),
|
.sset ()
|
.sset ()
|
// synopsys translate_on
|
// synopsys translate_on
|
);
|
);
|
defparam
|
defparam
|
lpm_ff_component.lpm_fftype = "DFF",
|
lpm_ff_component.lpm_fftype = "DFF",
|
lpm_ff_component.lpm_type = "LPM_FF",
|
lpm_ff_component.lpm_type = "LPM_FF",
|
lpm_ff_component.lpm_width = 1;
|
lpm_ff_component.lpm_width = 1;
|
endmodule
|
endmodule
|
// ============================================================
|
// ============================================================
|
// CNX file retrieval info
|
// CNX file retrieval info
|
// ============================================================
|
// ============================================================
|
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
|
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
|
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
|
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
|
// Retrieval info: PRIVATE: ASET NUMERIC "1"
|
// Retrieval info: PRIVATE: ASET NUMERIC "1"
|
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
|
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
|
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
|
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
|
// Retrieval info: PRIVATE: DFF NUMERIC "1"
|
// Retrieval info: PRIVATE: DFF NUMERIC "1"
|
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
|
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
|
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
|
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
|
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
|
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
|
// Retrieval info: PRIVATE: SSET NUMERIC "0"
|
// Retrieval info: PRIVATE: SSET NUMERIC "0"
|
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
|
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
|
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
|
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
|
// Retrieval info: PRIVATE: nBit NUMERIC "1"
|
// Retrieval info: PRIVATE: nBit NUMERIC "1"
|
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
|
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
|
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
|
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
|
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
|
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
|
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
|
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
|
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
|
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
|
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
|
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
|
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
|
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
|
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
|
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
|
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
|
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
|
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
|
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
|
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
|
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
|
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
|
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
|
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
|
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
|
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
|
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
|
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
|
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
|
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
|
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
|
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
|
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
|
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
|
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
|
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
|
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
|
// Retrieval info: LIB_FILE: lpm
|
// Retrieval info: LIB_FILE: lpm
|
// LATCH
|
// LATCH
|
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
|
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
|
module vl_latch ( d, le, q, clk);
|
module vl_latch ( d, le, q, clk);
|
input d, le;
|
input d, le;
|
output q;
|
output q;
|
input clk;
|
input clk;
|
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
|
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
|
endmodule
|
endmodule
|
module vl_shreg ( d, q, clk, rst);
|
module vl_shreg ( d, q, clk, rst);
|
parameter depth = 10;
|
parameter depth = 10;
|
input d;
|
input d;
|
output q;
|
output q;
|
input clk, rst;
|
input clk, rst;
|
reg [1:depth] dffs;
|
reg [1:depth] dffs;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
dffs <= {depth{1'b0}};
|
dffs <= {depth{1'b0}};
|
else
|
else
|
dffs <= {d,dffs[1:depth-1]};
|
dffs <= {d,dffs[1:depth-1]};
|
assign q = dffs[depth];
|
assign q = dffs[depth];
|
endmodule
|
endmodule
|
module vl_shreg_ce ( d, ce, q, clk, rst);
|
module vl_shreg_ce ( d, ce, q, clk, rst);
|
parameter depth = 10;
|
parameter depth = 10;
|
input d, ce;
|
input d, ce;
|
output q;
|
output q;
|
input clk, rst;
|
input clk, rst;
|
reg [1:depth] dffs;
|
reg [1:depth] dffs;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
dffs <= {depth{1'b0}};
|
dffs <= {depth{1'b0}};
|
else
|
else
|
if (ce)
|
if (ce)
|
dffs <= {d,dffs[1:depth-1]};
|
dffs <= {d,dffs[1:depth-1]};
|
assign q = dffs[depth];
|
assign q = dffs[depth];
|
endmodule
|
endmodule
|
module vl_delay ( d, q, clk, rst);
|
module vl_delay ( d, q, clk, rst);
|
parameter depth = 10;
|
parameter depth = 10;
|
input d;
|
input d;
|
output q;
|
output q;
|
input clk, rst;
|
input clk, rst;
|
reg [1:depth] dffs;
|
reg [1:depth] dffs;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
dffs <= {depth{1'b0}};
|
dffs <= {depth{1'b0}};
|
else
|
else
|
dffs <= {d,dffs[1:depth-1]};
|
dffs <= {d,dffs[1:depth-1]};
|
assign q = dffs[depth];
|
assign q = dffs[depth];
|
endmodule
|
endmodule
|
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
|
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
|
parameter depth = 10;
|
parameter depth = 10;
|
input d;
|
input d;
|
output q, emptyflag;
|
output q, emptyflag;
|
input clk, rst;
|
input clk, rst;
|
reg [1:depth] dffs;
|
reg [1:depth] dffs;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
dffs <= {depth{1'b0}};
|
dffs <= {depth{1'b0}};
|
else
|
else
|
dffs <= {d,dffs[1:depth-1]};
|
dffs <= {d,dffs[1:depth-1]};
|
assign q = dffs[depth];
|
assign q = dffs[depth];
|
assign emptyflag = !(|dffs);
|
assign emptyflag = !(|dffs);
|
endmodule
|
endmodule
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Logic functions ////
|
//// Logic functions ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
//// Logic functions such as multiplexers ////
|
//// Logic functions such as multiplexers ////
|
//// ////
|
//// ////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
//// - ////
|
//// - ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// ORSoC AB ////
|
//// ORSoC AB ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
|
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
|
parameter width = 32;
|
parameter width = 32;
|
parameter nr_of_ports = 4;
|
parameter nr_of_ports = 4;
|
input [width-1:0] a3, a2, a1, a0;
|
input [width-1:0] a3, a2, a1, a0;
|
input [nr_of_ports-1:0] sel;
|
input [nr_of_ports-1:0] sel;
|
output reg [width-1:0] dout;
|
output reg [width-1:0] dout;
|
reg [width-1:0] tmp [nr_of_ports-1:0];
|
wire [width-1:0] tmp [nr_of_ports-1:0];
|
integer i;
|
integer i;
|
// and
|
// and
|
assign tmp[0] = {width{sel[0]}} & a0;
|
assign tmp[0] = {width{sel[0]}} & a0;
|
assign tmp[1] = {width{sel[1]}} & a1;
|
assign tmp[1] = {width{sel[1]}} & a1;
|
assign tmp[2] = {width{sel[2]}} & a2;
|
assign tmp[2] = {width{sel[2]}} & a2;
|
assign tmp[3] = {width{sel[3]}} & a3;
|
assign tmp[3] = {width{sel[3]}} & a3;
|
// or
|
// or
|
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
|
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
|
endmodule
|
endmodule
|
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
|
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
|
parameter width = 32;
|
parameter width = 32;
|
parameter nr_of_ports = 5;
|
parameter nr_of_ports = 5;
|
input [width-1:0] a4, a3, a2, a1, a0;
|
input [width-1:0] a4, a3, a2, a1, a0;
|
input [nr_of_ports-1:0] sel;
|
input [nr_of_ports-1:0] sel;
|
output reg [width-1:0] dout;
|
output reg [width-1:0] dout;
|
reg [width-1:0] tmp [nr_of_ports-1:0];
|
wire [width-1:0] tmp [nr_of_ports-1:0];
|
integer i;
|
integer i;
|
// and
|
// and
|
assign tmp[0] = {width{sel[0]}} & a0;
|
assign tmp[0] = {width{sel[0]}} & a0;
|
assign tmp[1] = {width{sel[1]}} & a1;
|
assign tmp[1] = {width{sel[1]}} & a1;
|
assign tmp[2] = {width{sel[2]}} & a2;
|
assign tmp[2] = {width{sel[2]}} & a2;
|
assign tmp[3] = {width{sel[3]}} & a3;
|
assign tmp[3] = {width{sel[3]}} & a3;
|
assign tmp[4] = {width{sel[4]}} & a4;
|
assign tmp[4] = {width{sel[4]}} & a4;
|
// or
|
// or
|
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
|
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
|
endmodule
|
endmodule
|
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
|
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
|
parameter width = 32;
|
parameter width = 32;
|
parameter nr_of_ports = 6;
|
parameter nr_of_ports = 6;
|
input [width-1:0] a5, a4, a3, a2, a1, a0;
|
input [width-1:0] a5, a4, a3, a2, a1, a0;
|
input [nr_of_ports-1:0] sel;
|
input [nr_of_ports-1:0] sel;
|
output reg [width-1:0] dout;
|
output reg [width-1:0] dout;
|
reg [width-1:0] tmp [nr_of_ports-1:0];
|
wire [width-1:0] tmp [nr_of_ports-1:0];
|
integer i;
|
integer i;
|
// and
|
// and
|
assign tmp[0] = {width{sel[0]}} & a0;
|
assign tmp[0] = {width{sel[0]}} & a0;
|
assign tmp[1] = {width{sel[1]}} & a1;
|
assign tmp[1] = {width{sel[1]}} & a1;
|
assign tmp[2] = {width{sel[2]}} & a2;
|
assign tmp[2] = {width{sel[2]}} & a2;
|
assign tmp[3] = {width{sel[3]}} & a3;
|
assign tmp[3] = {width{sel[3]}} & a3;
|
assign tmp[4] = {width{sel[4]}} & a4;
|
assign tmp[4] = {width{sel[4]}} & a4;
|
assign tmp[5] = {width{sel[5]}} & a5;
|
assign tmp[5] = {width{sel[5]}} & a5;
|
// or
|
// or
|
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
|
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
|
endmodule
|
endmodule
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Versatile counter ////
|
//// Versatile counter ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
//// counter ////
|
//// counter ////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
//// - add LFSR with more taps ////
|
//// - add LFSR with more taps ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// ORSoC AB ////
|
//// ORSoC AB ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
// binary counter
|
// binary counter
|
module vl_cnt_bin_ce ( cke, q, rst, clk);
|
module vl_cnt_bin_ce ( cke, q, rst, clk);
|
parameter length = 4;
|
parameter length = 4;
|
input cke;
|
input cke;
|
output [length:1] q;
|
output [length:1] q;
|
input rst;
|
input rst;
|
input clk;
|
input clk;
|
parameter clear_value = 0;
|
parameter clear_value = 0;
|
parameter set_value = 1;
|
parameter set_value = 1;
|
parameter wrap_value = 0;
|
parameter wrap_value = 0;
|
parameter level1_value = 15;
|
parameter level1_value = 15;
|
reg [length:1] qi;
|
reg [length:1] qi;
|
wire [length:1] q_next;
|
wire [length:1] q_next;
|
assign q_next = qi + {{length-1{1'b0}},1'b1};
|
assign q_next = qi + {{length-1{1'b0}},1'b1};
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
qi <= {length{1'b0}};
|
qi <= {length{1'b0}};
|
else
|
else
|
if (cke)
|
if (cke)
|
qi <= q_next;
|
qi <= q_next;
|
assign q = qi;
|
assign q = qi;
|
endmodule
|
endmodule
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Versatile counter ////
|
//// Versatile counter ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
//// counter ////
|
//// counter ////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
//// - add LFSR with more taps ////
|
//// - add LFSR with more taps ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// ORSoC AB ////
|
//// ORSoC AB ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
// binary counter
|
// binary counter
|
module vl_cnt_bin_ce_clear ( clear, cke, q, rst, clk);
|
module vl_cnt_bin_ce_clear ( clear, cke, q, rst, clk);
|
parameter length = 4;
|
parameter length = 4;
|
input clear;
|
input clear;
|
input cke;
|
input cke;
|
output [length:1] q;
|
output [length:1] q;
|
input rst;
|
input rst;
|
input clk;
|
input clk;
|
parameter clear_value = 0;
|
parameter clear_value = 0;
|
parameter set_value = 1;
|
parameter set_value = 1;
|
parameter wrap_value = 0;
|
parameter wrap_value = 0;
|
parameter level1_value = 15;
|
parameter level1_value = 15;
|
reg [length:1] qi;
|
reg [length:1] qi;
|
wire [length:1] q_next;
|
wire [length:1] q_next;
|
assign q_next = clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
|
assign q_next = clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
qi <= {length{1'b0}};
|
qi <= {length{1'b0}};
|
else
|
else
|
if (cke)
|
if (cke)
|
qi <= q_next;
|
qi <= q_next;
|
assign q = qi;
|
assign q = qi;
|
endmodule
|
endmodule
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Versatile counter ////
|
//// Versatile counter ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
//// counter ////
|
//// counter ////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
//// - add LFSR with more taps ////
|
//// - add LFSR with more taps ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// ORSoC AB ////
|
//// ORSoC AB ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
// binary counter
|
// binary counter
|
module vl_cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
|
module vl_cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
|
parameter length = 4;
|
parameter length = 4;
|
input clear;
|
input clear;
|
input set;
|
input set;
|
input cke;
|
input cke;
|
input rew;
|
input rew;
|
output [length:1] q;
|
output [length:1] q;
|
input rst;
|
input rst;
|
input clk;
|
input clk;
|
parameter clear_value = 0;
|
parameter clear_value = 0;
|
parameter set_value = 1;
|
parameter set_value = 1;
|
parameter wrap_value = 0;
|
parameter wrap_value = 0;
|
parameter level1_value = 15;
|
parameter level1_value = 15;
|
reg [length:1] qi;
|
reg [length:1] qi;
|
wire [length:1] q_next, q_next_fw, q_next_rew;
|
wire [length:1] q_next, q_next_fw, q_next_rew;
|
assign q_next_fw = clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
|
assign q_next_fw = clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
|
assign q_next_rew = clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
|
assign q_next_rew = clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
|
assign q_next = rew ? q_next_rew : q_next_fw;
|
assign q_next = rew ? q_next_rew : q_next_fw;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
qi <= {length{1'b0}};
|
qi <= {length{1'b0}};
|
else
|
else
|
if (cke)
|
if (cke)
|
qi <= q_next;
|
qi <= q_next;
|
assign q = qi;
|
assign q = qi;
|
endmodule
|
endmodule
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Versatile counter ////
|
//// Versatile counter ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
//// counter ////
|
//// counter ////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
//// - add LFSR with more taps ////
|
//// - add LFSR with more taps ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// ORSoC AB ////
|
//// ORSoC AB ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
// binary counter
|
// binary counter
|
module vl_cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
|
module vl_cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
|
parameter length = 4;
|
parameter length = 4;
|
input cke;
|
input cke;
|
input rew;
|
input rew;
|
output reg level1;
|
output reg level1;
|
input rst;
|
input rst;
|
input clk;
|
input clk;
|
parameter clear_value = 0;
|
parameter clear_value = 0;
|
parameter set_value = 1;
|
parameter set_value = 1;
|
parameter wrap_value = 1;
|
parameter wrap_value = 1;
|
parameter level1_value = 15;
|
parameter level1_value = 15;
|
reg [length:1] qi;
|
reg [length:1] qi;
|
wire [length:1] q_next, q_next_fw, q_next_rew;
|
wire [length:1] q_next, q_next_fw, q_next_rew;
|
assign q_next_fw = qi + {{length-1{1'b0}},1'b1};
|
assign q_next_fw = qi + {{length-1{1'b0}},1'b1};
|
assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
|
assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
|
assign q_next = rew ? q_next_rew : q_next_fw;
|
assign q_next = rew ? q_next_rew : q_next_fw;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
qi <= {length{1'b0}};
|
qi <= {length{1'b0}};
|
else
|
else
|
if (cke)
|
if (cke)
|
qi <= q_next;
|
qi <= q_next;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
level1 <= 1'b0;
|
level1 <= 1'b0;
|
else
|
else
|
if (cke)
|
if (cke)
|
if (q_next == level1_value)
|
if (q_next == level1_value)
|
level1 <= 1'b1;
|
level1 <= 1'b1;
|
else if (qi == level1_value & rew)
|
else if (qi == level1_value & rew)
|
level1 <= 1'b0;
|
level1 <= 1'b0;
|
endmodule
|
endmodule
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Versatile counter ////
|
//// Versatile counter ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
//// counter ////
|
//// counter ////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
//// - add LFSR with more taps ////
|
//// - add LFSR with more taps ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// ORSoC AB ////
|
//// ORSoC AB ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
// LFSR counter
|
// LFSR counter
|
module vl_cnt_lfsr_zq ( zq, rst, clk);
|
module vl_cnt_lfsr_zq ( zq, rst, clk);
|
parameter length = 4;
|
parameter length = 4;
|
output reg zq;
|
output reg zq;
|
input rst;
|
input rst;
|
input clk;
|
input clk;
|
parameter clear_value = 0;
|
parameter clear_value = 0;
|
parameter set_value = 1;
|
parameter set_value = 1;
|
parameter wrap_value = 8;
|
parameter wrap_value = 8;
|
parameter level1_value = 15;
|
parameter level1_value = 15;
|
reg [length:1] qi;
|
reg [length:1] qi;
|
reg lfsr_fb;
|
reg lfsr_fb;
|
wire [length:1] q_next;
|
wire [length:1] q_next;
|
reg [32:1] polynom;
|
reg [32:1] polynom;
|
integer i;
|
integer i;
|
always @ (qi)
|
always @ (qi)
|
begin
|
begin
|
case (length)
|
case (length)
|
2: polynom = 32'b11; // 0x3
|
2: polynom = 32'b11; // 0x3
|
3: polynom = 32'b110; // 0x6
|
3: polynom = 32'b110; // 0x6
|
4: polynom = 32'b1100; // 0xC
|
4: polynom = 32'b1100; // 0xC
|
5: polynom = 32'b10100; // 0x14
|
5: polynom = 32'b10100; // 0x14
|
6: polynom = 32'b110000; // 0x30
|
6: polynom = 32'b110000; // 0x30
|
7: polynom = 32'b1100000; // 0x60
|
7: polynom = 32'b1100000; // 0x60
|
8: polynom = 32'b10111000; // 0xb8
|
8: polynom = 32'b10111000; // 0xb8
|
9: polynom = 32'b100010000; // 0x110
|
9: polynom = 32'b100010000; // 0x110
|
10: polynom = 32'b1001000000; // 0x240
|
10: polynom = 32'b1001000000; // 0x240
|
11: polynom = 32'b10100000000; // 0x500
|
11: polynom = 32'b10100000000; // 0x500
|
12: polynom = 32'b100000101001; // 0x829
|
12: polynom = 32'b100000101001; // 0x829
|
13: polynom = 32'b1000000001100; // 0x100C
|
13: polynom = 32'b1000000001100; // 0x100C
|
14: polynom = 32'b10000000010101; // 0x2015
|
14: polynom = 32'b10000000010101; // 0x2015
|
15: polynom = 32'b110000000000000; // 0x6000
|
15: polynom = 32'b110000000000000; // 0x6000
|
16: polynom = 32'b1101000000001000; // 0xD008
|
16: polynom = 32'b1101000000001000; // 0xD008
|
17: polynom = 32'b10010000000000000; // 0x12000
|
17: polynom = 32'b10010000000000000; // 0x12000
|
18: polynom = 32'b100000010000000000; // 0x20400
|
18: polynom = 32'b100000010000000000; // 0x20400
|
19: polynom = 32'b1000000000000100011; // 0x40023
|
19: polynom = 32'b1000000000000100011; // 0x40023
|
20: polynom = 32'b10000010000000000000; // 0x82000
|
20: polynom = 32'b10000010000000000000; // 0x82000
|
21: polynom = 32'b101000000000000000000; // 0x140000
|
21: polynom = 32'b101000000000000000000; // 0x140000
|
22: polynom = 32'b1100000000000000000000; // 0x300000
|
22: polynom = 32'b1100000000000000000000; // 0x300000
|
23: polynom = 32'b10000100000000000000000; // 0x420000
|
23: polynom = 32'b10000100000000000000000; // 0x420000
|
24: polynom = 32'b111000010000000000000000; // 0xE10000
|
24: polynom = 32'b111000010000000000000000; // 0xE10000
|
25: polynom = 32'b1001000000000000000000000; // 0x1200000
|
25: polynom = 32'b1001000000000000000000000; // 0x1200000
|
26: polynom = 32'b10000000000000000000100011; // 0x2000023
|
26: polynom = 32'b10000000000000000000100011; // 0x2000023
|
27: polynom = 32'b100000000000000000000010011; // 0x4000013
|
27: polynom = 32'b100000000000000000000010011; // 0x4000013
|
28: polynom = 32'b1100100000000000000000000000; // 0xC800000
|
28: polynom = 32'b1100100000000000000000000000; // 0xC800000
|
29: polynom = 32'b10100000000000000000000000000; // 0x14000000
|
29: polynom = 32'b10100000000000000000000000000; // 0x14000000
|
30: polynom = 32'b100000000000000000000000101001; // 0x20000029
|
30: polynom = 32'b100000000000000000000000101001; // 0x20000029
|
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000
|
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000
|
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
|
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
|
default: polynom = 32'b0;
|
default: polynom = 32'b0;
|
endcase
|
endcase
|
lfsr_fb = qi[length];
|
lfsr_fb = qi[length];
|
for (i=length-1; i>=1; i=i-1) begin
|
for (i=length-1; i>=1; i=i-1) begin
|
if (polynom[i])
|
if (polynom[i])
|
lfsr_fb = lfsr_fb ~^ qi[i];
|
lfsr_fb = lfsr_fb ~^ qi[i];
|
end
|
end
|
end
|
end
|
assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
|
assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
qi <= {length{1'b0}};
|
qi <= {length{1'b0}};
|
else
|
else
|
qi <= q_next;
|
qi <= q_next;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
zq <= 1'b1;
|
zq <= 1'b1;
|
else
|
else
|
zq <= q_next == {length{1'b0}};
|
zq <= q_next == {length{1'b0}};
|
endmodule
|
endmodule
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Versatile counter ////
|
//// Versatile counter ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
//// counter ////
|
//// counter ////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
//// - add LFSR with more taps ////
|
//// - add LFSR with more taps ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// ORSoC AB ////
|
//// ORSoC AB ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
// LFSR counter
|
// LFSR counter
|
module vl_cnt_lfsr_ce_zq ( cke, zq, rst, clk);
|
module vl_cnt_lfsr_ce_zq ( cke, zq, rst, clk);
|
parameter length = 4;
|
parameter length = 4;
|
input cke;
|
input cke;
|
output reg zq;
|
output reg zq;
|
input rst;
|
input rst;
|
input clk;
|
input clk;
|
parameter clear_value = 0;
|
parameter clear_value = 0;
|
parameter set_value = 1;
|
parameter set_value = 1;
|
parameter wrap_value = 8;
|
parameter wrap_value = 8;
|
parameter level1_value = 15;
|
parameter level1_value = 15;
|
reg [length:1] qi;
|
reg [length:1] qi;
|
reg lfsr_fb;
|
reg lfsr_fb;
|
wire [length:1] q_next;
|
wire [length:1] q_next;
|
reg [32:1] polynom;
|
reg [32:1] polynom;
|
integer i;
|
integer i;
|
always @ (qi)
|
always @ (qi)
|
begin
|
begin
|
case (length)
|
case (length)
|
2: polynom = 32'b11; // 0x3
|
2: polynom = 32'b11; // 0x3
|
3: polynom = 32'b110; // 0x6
|
3: polynom = 32'b110; // 0x6
|
4: polynom = 32'b1100; // 0xC
|
4: polynom = 32'b1100; // 0xC
|
5: polynom = 32'b10100; // 0x14
|
5: polynom = 32'b10100; // 0x14
|
6: polynom = 32'b110000; // 0x30
|
6: polynom = 32'b110000; // 0x30
|
7: polynom = 32'b1100000; // 0x60
|
7: polynom = 32'b1100000; // 0x60
|
8: polynom = 32'b10111000; // 0xb8
|
8: polynom = 32'b10111000; // 0xb8
|
9: polynom = 32'b100010000; // 0x110
|
9: polynom = 32'b100010000; // 0x110
|
10: polynom = 32'b1001000000; // 0x240
|
10: polynom = 32'b1001000000; // 0x240
|
11: polynom = 32'b10100000000; // 0x500
|
11: polynom = 32'b10100000000; // 0x500
|
12: polynom = 32'b100000101001; // 0x829
|
12: polynom = 32'b100000101001; // 0x829
|
13: polynom = 32'b1000000001100; // 0x100C
|
13: polynom = 32'b1000000001100; // 0x100C
|
14: polynom = 32'b10000000010101; // 0x2015
|
14: polynom = 32'b10000000010101; // 0x2015
|
15: polynom = 32'b110000000000000; // 0x6000
|
15: polynom = 32'b110000000000000; // 0x6000
|
16: polynom = 32'b1101000000001000; // 0xD008
|
16: polynom = 32'b1101000000001000; // 0xD008
|
17: polynom = 32'b10010000000000000; // 0x12000
|
17: polynom = 32'b10010000000000000; // 0x12000
|
18: polynom = 32'b100000010000000000; // 0x20400
|
18: polynom = 32'b100000010000000000; // 0x20400
|
19: polynom = 32'b1000000000000100011; // 0x40023
|
19: polynom = 32'b1000000000000100011; // 0x40023
|
20: polynom = 32'b10000010000000000000; // 0x82000
|
20: polynom = 32'b10000010000000000000; // 0x82000
|
21: polynom = 32'b101000000000000000000; // 0x140000
|
21: polynom = 32'b101000000000000000000; // 0x140000
|
22: polynom = 32'b1100000000000000000000; // 0x300000
|
22: polynom = 32'b1100000000000000000000; // 0x300000
|
23: polynom = 32'b10000100000000000000000; // 0x420000
|
23: polynom = 32'b10000100000000000000000; // 0x420000
|
24: polynom = 32'b111000010000000000000000; // 0xE10000
|
24: polynom = 32'b111000010000000000000000; // 0xE10000
|
25: polynom = 32'b1001000000000000000000000; // 0x1200000
|
25: polynom = 32'b1001000000000000000000000; // 0x1200000
|
26: polynom = 32'b10000000000000000000100011; // 0x2000023
|
26: polynom = 32'b10000000000000000000100011; // 0x2000023
|
27: polynom = 32'b100000000000000000000010011; // 0x4000013
|
27: polynom = 32'b100000000000000000000010011; // 0x4000013
|
28: polynom = 32'b1100100000000000000000000000; // 0xC800000
|
28: polynom = 32'b1100100000000000000000000000; // 0xC800000
|
29: polynom = 32'b10100000000000000000000000000; // 0x14000000
|
29: polynom = 32'b10100000000000000000000000000; // 0x14000000
|
30: polynom = 32'b100000000000000000000000101001; // 0x20000029
|
30: polynom = 32'b100000000000000000000000101001; // 0x20000029
|
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000
|
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000
|
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
|
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
|
default: polynom = 32'b0;
|
default: polynom = 32'b0;
|
endcase
|
endcase
|
lfsr_fb = qi[length];
|
lfsr_fb = qi[length];
|
for (i=length-1; i>=1; i=i-1) begin
|
for (i=length-1; i>=1; i=i-1) begin
|
if (polynom[i])
|
if (polynom[i])
|
lfsr_fb = lfsr_fb ~^ qi[i];
|
lfsr_fb = lfsr_fb ~^ qi[i];
|
end
|
end
|
end
|
end
|
assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
|
assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
qi <= {length{1'b0}};
|
qi <= {length{1'b0}};
|
else
|
else
|
if (cke)
|
if (cke)
|
qi <= q_next;
|
qi <= q_next;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
zq <= 1'b1;
|
zq <= 1'b1;
|
else
|
else
|
if (cke)
|
if (cke)
|
zq <= q_next == {length{1'b0}};
|
zq <= q_next == {length{1'b0}};
|
endmodule
|
endmodule
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Versatile counter ////
|
//// Versatile counter ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
//// counter ////
|
//// counter ////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
//// - add LFSR with more taps ////
|
//// - add LFSR with more taps ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// ORSoC AB ////
|
//// ORSoC AB ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
// LFSR counter
|
// LFSR counter
|
module vl_cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
|
module vl_cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
|
parameter length = 4;
|
parameter length = 4;
|
input cke;
|
input cke;
|
input rew;
|
input rew;
|
output reg level1;
|
output reg level1;
|
input rst;
|
input rst;
|
input clk;
|
input clk;
|
parameter clear_value = 0;
|
parameter clear_value = 0;
|
parameter set_value = 1;
|
parameter set_value = 1;
|
parameter wrap_value = 8;
|
parameter wrap_value = 8;
|
parameter level1_value = 15;
|
parameter level1_value = 15;
|
reg [length:1] qi;
|
reg [length:1] qi;
|
reg lfsr_fb, lfsr_fb_rew;
|
reg lfsr_fb, lfsr_fb_rew;
|
wire [length:1] q_next, q_next_fw, q_next_rew;
|
wire [length:1] q_next, q_next_fw, q_next_rew;
|
reg [32:1] polynom_rew;
|
reg [32:1] polynom_rew;
|
integer j;
|
integer j;
|
reg [32:1] polynom;
|
reg [32:1] polynom;
|
integer i;
|
integer i;
|
always @ (qi)
|
always @ (qi)
|
begin
|
begin
|
case (length)
|
case (length)
|
2: polynom = 32'b11; // 0x3
|
2: polynom = 32'b11; // 0x3
|
3: polynom = 32'b110; // 0x6
|
3: polynom = 32'b110; // 0x6
|
4: polynom = 32'b1100; // 0xC
|
4: polynom = 32'b1100; // 0xC
|
5: polynom = 32'b10100; // 0x14
|
5: polynom = 32'b10100; // 0x14
|
6: polynom = 32'b110000; // 0x30
|
6: polynom = 32'b110000; // 0x30
|
7: polynom = 32'b1100000; // 0x60
|
7: polynom = 32'b1100000; // 0x60
|
8: polynom = 32'b10111000; // 0xb8
|
8: polynom = 32'b10111000; // 0xb8
|
9: polynom = 32'b100010000; // 0x110
|
9: polynom = 32'b100010000; // 0x110
|
10: polynom = 32'b1001000000; // 0x240
|
10: polynom = 32'b1001000000; // 0x240
|
11: polynom = 32'b10100000000; // 0x500
|
11: polynom = 32'b10100000000; // 0x500
|
12: polynom = 32'b100000101001; // 0x829
|
12: polynom = 32'b100000101001; // 0x829
|
13: polynom = 32'b1000000001100; // 0x100C
|
13: polynom = 32'b1000000001100; // 0x100C
|
14: polynom = 32'b10000000010101; // 0x2015
|
14: polynom = 32'b10000000010101; // 0x2015
|
15: polynom = 32'b110000000000000; // 0x6000
|
15: polynom = 32'b110000000000000; // 0x6000
|
16: polynom = 32'b1101000000001000; // 0xD008
|
16: polynom = 32'b1101000000001000; // 0xD008
|
17: polynom = 32'b10010000000000000; // 0x12000
|
17: polynom = 32'b10010000000000000; // 0x12000
|
18: polynom = 32'b100000010000000000; // 0x20400
|
18: polynom = 32'b100000010000000000; // 0x20400
|
19: polynom = 32'b1000000000000100011; // 0x40023
|
19: polynom = 32'b1000000000000100011; // 0x40023
|
20: polynom = 32'b10000010000000000000; // 0x82000
|
20: polynom = 32'b10000010000000000000; // 0x82000
|
21: polynom = 32'b101000000000000000000; // 0x140000
|
21: polynom = 32'b101000000000000000000; // 0x140000
|
22: polynom = 32'b1100000000000000000000; // 0x300000
|
22: polynom = 32'b1100000000000000000000; // 0x300000
|
23: polynom = 32'b10000100000000000000000; // 0x420000
|
23: polynom = 32'b10000100000000000000000; // 0x420000
|
24: polynom = 32'b111000010000000000000000; // 0xE10000
|
24: polynom = 32'b111000010000000000000000; // 0xE10000
|
25: polynom = 32'b1001000000000000000000000; // 0x1200000
|
25: polynom = 32'b1001000000000000000000000; // 0x1200000
|
26: polynom = 32'b10000000000000000000100011; // 0x2000023
|
26: polynom = 32'b10000000000000000000100011; // 0x2000023
|
27: polynom = 32'b100000000000000000000010011; // 0x4000013
|
27: polynom = 32'b100000000000000000000010011; // 0x4000013
|
28: polynom = 32'b1100100000000000000000000000; // 0xC800000
|
28: polynom = 32'b1100100000000000000000000000; // 0xC800000
|
29: polynom = 32'b10100000000000000000000000000; // 0x14000000
|
29: polynom = 32'b10100000000000000000000000000; // 0x14000000
|
30: polynom = 32'b100000000000000000000000101001; // 0x20000029
|
30: polynom = 32'b100000000000000000000000101001; // 0x20000029
|
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000
|
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000
|
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
|
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
|
default: polynom = 32'b0;
|
default: polynom = 32'b0;
|
endcase
|
endcase
|
lfsr_fb = qi[length];
|
lfsr_fb = qi[length];
|
for (i=length-1; i>=1; i=i-1) begin
|
for (i=length-1; i>=1; i=i-1) begin
|
if (polynom[i])
|
if (polynom[i])
|
lfsr_fb = lfsr_fb ~^ qi[i];
|
lfsr_fb = lfsr_fb ~^ qi[i];
|
end
|
end
|
end
|
end
|
assign q_next_fw = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
|
assign q_next_fw = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
|
always @ (qi)
|
always @ (qi)
|
begin
|
begin
|
case (length)
|
case (length)
|
2: polynom_rew = 32'b11;
|
2: polynom_rew = 32'b11;
|
3: polynom_rew = 32'b110;
|
3: polynom_rew = 32'b110;
|
4: polynom_rew = 32'b1100;
|
4: polynom_rew = 32'b1100;
|
5: polynom_rew = 32'b10100;
|
5: polynom_rew = 32'b10100;
|
6: polynom_rew = 32'b110000;
|
6: polynom_rew = 32'b110000;
|
7: polynom_rew = 32'b1100000;
|
7: polynom_rew = 32'b1100000;
|
8: polynom_rew = 32'b10111000;
|
8: polynom_rew = 32'b10111000;
|
9: polynom_rew = 32'b100010000;
|
9: polynom_rew = 32'b100010000;
|
10: polynom_rew = 32'b1001000000;
|
10: polynom_rew = 32'b1001000000;
|
11: polynom_rew = 32'b10100000000;
|
11: polynom_rew = 32'b10100000000;
|
12: polynom_rew = 32'b100000101001;
|
12: polynom_rew = 32'b100000101001;
|
13: polynom_rew = 32'b1000000001100;
|
13: polynom_rew = 32'b1000000001100;
|
14: polynom_rew = 32'b10000000010101;
|
14: polynom_rew = 32'b10000000010101;
|
15: polynom_rew = 32'b110000000000000;
|
15: polynom_rew = 32'b110000000000000;
|
16: polynom_rew = 32'b1101000000001000;
|
16: polynom_rew = 32'b1101000000001000;
|
17: polynom_rew = 32'b10010000000000000;
|
17: polynom_rew = 32'b10010000000000000;
|
18: polynom_rew = 32'b100000010000000000;
|
18: polynom_rew = 32'b100000010000000000;
|
19: polynom_rew = 32'b1000000000000100011;
|
19: polynom_rew = 32'b1000000000000100011;
|
20: polynom_rew = 32'b10000010000000000000;
|
20: polynom_rew = 32'b10000010000000000000;
|
21: polynom_rew = 32'b101000000000000000000;
|
21: polynom_rew = 32'b101000000000000000000;
|
22: polynom_rew = 32'b1100000000000000000000;
|
22: polynom_rew = 32'b1100000000000000000000;
|
23: polynom_rew = 32'b10000100000000000000000;
|
23: polynom_rew = 32'b10000100000000000000000;
|
24: polynom_rew = 32'b111000010000000000000000;
|
24: polynom_rew = 32'b111000010000000000000000;
|
25: polynom_rew = 32'b1001000000000000000000000;
|
25: polynom_rew = 32'b1001000000000000000000000;
|
26: polynom_rew = 32'b10000000000000000000100011;
|
26: polynom_rew = 32'b10000000000000000000100011;
|
27: polynom_rew = 32'b100000000000000000000010011;
|
27: polynom_rew = 32'b100000000000000000000010011;
|
28: polynom_rew = 32'b1100100000000000000000000000;
|
28: polynom_rew = 32'b1100100000000000000000000000;
|
29: polynom_rew = 32'b10100000000000000000000000000;
|
29: polynom_rew = 32'b10100000000000000000000000000;
|
30: polynom_rew = 32'b100000000000000000000000101001;
|
30: polynom_rew = 32'b100000000000000000000000101001;
|
31: polynom_rew = 32'b1001000000000000000000000000000;
|
31: polynom_rew = 32'b1001000000000000000000000000000;
|
32: polynom_rew = 32'b10000000001000000000000000000011;
|
32: polynom_rew = 32'b10000000001000000000000000000011;
|
default: polynom_rew = 32'b0;
|
default: polynom_rew = 32'b0;
|
endcase
|
endcase
|
// rotate left
|
// rotate left
|
polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
|
polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
|
lfsr_fb_rew = qi[length];
|
lfsr_fb_rew = qi[length];
|
for (i=length-1; i>=1; i=i-1) begin
|
for (i=length-1; i>=1; i=i-1) begin
|
if (polynom_rew[i])
|
if (polynom_rew[i])
|
lfsr_fb_rew = lfsr_fb_rew ~^ qi[i];
|
lfsr_fb_rew = lfsr_fb_rew ~^ qi[i];
|
end
|
end
|
end
|
end
|
assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
|
assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
|
assign q_next = rew ? q_next_rew : q_next_fw;
|
assign q_next = rew ? q_next_rew : q_next_fw;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
qi <= {length{1'b0}};
|
qi <= {length{1'b0}};
|
else
|
else
|
if (cke)
|
if (cke)
|
qi <= q_next;
|
qi <= q_next;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
level1 <= 1'b0;
|
level1 <= 1'b0;
|
else
|
else
|
if (cke)
|
if (cke)
|
if (q_next == level1_value)
|
if (q_next == level1_value)
|
level1 <= 1'b1;
|
level1 <= 1'b1;
|
else if (qi == level1_value & rew)
|
else if (qi == level1_value & rew)
|
level1 <= 1'b0;
|
level1 <= 1'b0;
|
endmodule
|
endmodule
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Versatile counter ////
|
//// Versatile counter ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
//// counter ////
|
//// counter ////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
//// - add LFSR with more taps ////
|
//// - add LFSR with more taps ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// ORSoC AB ////
|
//// ORSoC AB ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
// GRAY counter
|
// GRAY counter
|
module vl_cnt_gray ( q, rst, clk);
|
module vl_cnt_gray ( q, rst, clk);
|
parameter length = 4;
|
parameter length = 4;
|
output reg [length:1] q;
|
output reg [length:1] q;
|
input rst;
|
input rst;
|
input clk;
|
input clk;
|
parameter clear_value = 0;
|
parameter clear_value = 0;
|
parameter set_value = 1;
|
parameter set_value = 1;
|
parameter wrap_value = 8;
|
parameter wrap_value = 8;
|
parameter level1_value = 15;
|
parameter level1_value = 15;
|
reg [length:1] qi;
|
reg [length:1] qi;
|
wire [length:1] q_next;
|
wire [length:1] q_next;
|
assign q_next = qi + {{length-1{1'b0}},1'b1};
|
assign q_next = qi + {{length-1{1'b0}},1'b1};
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
qi <= {length{1'b0}};
|
qi <= {length{1'b0}};
|
else
|
else
|
qi <= q_next;
|
qi <= q_next;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
q <= {length{1'b0}};
|
q <= {length{1'b0}};
|
else
|
else
|
q <= (q_next>>1) ^ q_next;
|
q <= (q_next>>1) ^ q_next;
|
endmodule
|
endmodule
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Versatile counter ////
|
//// Versatile counter ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
//// counter ////
|
//// counter ////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
//// - add LFSR with more taps ////
|
//// - add LFSR with more taps ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// ORSoC AB ////
|
//// ORSoC AB ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
// GRAY counter
|
// GRAY counter
|
module vl_cnt_gray_ce ( cke, q, rst, clk);
|
module vl_cnt_gray_ce ( cke, q, rst, clk);
|
parameter length = 4;
|
parameter length = 4;
|
input cke;
|
input cke;
|
output reg [length:1] q;
|
output reg [length:1] q;
|
input rst;
|
input rst;
|
input clk;
|
input clk;
|
parameter clear_value = 0;
|
parameter clear_value = 0;
|
parameter set_value = 1;
|
parameter set_value = 1;
|
parameter wrap_value = 8;
|
parameter wrap_value = 8;
|
parameter level1_value = 15;
|
parameter level1_value = 15;
|
reg [length:1] qi;
|
reg [length:1] qi;
|
wire [length:1] q_next;
|
wire [length:1] q_next;
|
assign q_next = qi + {{length-1{1'b0}},1'b1};
|
assign q_next = qi + {{length-1{1'b0}},1'b1};
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
qi <= {length{1'b0}};
|
qi <= {length{1'b0}};
|
else
|
else
|
if (cke)
|
if (cke)
|
qi <= q_next;
|
qi <= q_next;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
q <= {length{1'b0}};
|
q <= {length{1'b0}};
|
else
|
else
|
if (cke)
|
if (cke)
|
q <= (q_next>>1) ^ q_next;
|
q <= (q_next>>1) ^ q_next;
|
endmodule
|
endmodule
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Versatile counter ////
|
//// Versatile counter ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
//// counter ////
|
//// counter ////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
//// - add LFSR with more taps ////
|
//// - add LFSR with more taps ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// ORSoC AB ////
|
//// ORSoC AB ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
// GRAY counter
|
// GRAY counter
|
module vl_cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
|
module vl_cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
|
parameter length = 4;
|
parameter length = 4;
|
input cke;
|
input cke;
|
output reg [length:1] q;
|
output reg [length:1] q;
|
output [length:1] q_bin;
|
output [length:1] q_bin;
|
input rst;
|
input rst;
|
input clk;
|
input clk;
|
parameter clear_value = 0;
|
parameter clear_value = 0;
|
parameter set_value = 1;
|
parameter set_value = 1;
|
parameter wrap_value = 8;
|
parameter wrap_value = 8;
|
parameter level1_value = 15;
|
parameter level1_value = 15;
|
reg [length:1] qi;
|
reg [length:1] qi;
|
wire [length:1] q_next;
|
wire [length:1] q_next;
|
assign q_next = qi + {{length-1{1'b0}},1'b1};
|
assign q_next = qi + {{length-1{1'b0}},1'b1};
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
qi <= {length{1'b0}};
|
qi <= {length{1'b0}};
|
else
|
else
|
if (cke)
|
if (cke)
|
qi <= q_next;
|
qi <= q_next;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
q <= {length{1'b0}};
|
q <= {length{1'b0}};
|
else
|
else
|
if (cke)
|
if (cke)
|
q <= (q_next>>1) ^ q_next;
|
q <= (q_next>>1) ^ q_next;
|
assign q_bin = qi;
|
assign q_bin = qi;
|
endmodule
|
endmodule
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Versatile library, counters ////
|
//// Versatile library, counters ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
//// counters ////
|
//// counters ////
|
//// ////
|
//// ////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
//// - add more counters ////
|
//// - add more counters ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// ORSoC AB ////
|
//// ORSoC AB ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
module vl_cnt_shreg_wrap ( q, rst, clk);
|
module vl_cnt_shreg_wrap ( q, rst, clk);
|
parameter length = 4;
|
parameter length = 4;
|
output reg [0:length-1] q;
|
output reg [0:length-1] q;
|
input rst;
|
input rst;
|
input clk;
|
input clk;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
q <= {1'b1,{length-1{1'b0}}};
|
q <= {1'b1,{length-1{1'b0}}};
|
else
|
else
|
q <= {q[length-1],q[0:length-2]};
|
q <= {q[length-1],q[0:length-2]};
|
endmodule
|
endmodule
|
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
|
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
|
parameter length = 4;
|
parameter length = 4;
|
input cke;
|
input cke;
|
output reg [0:length-1] q;
|
output reg [0:length-1] q;
|
input rst;
|
input rst;
|
input clk;
|
input clk;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
q <= {1'b1,{length-1{1'b0}}};
|
q <= {1'b1,{length-1{1'b0}}};
|
else
|
else
|
if (cke)
|
if (cke)
|
q <= {q[length-1],q[0:length-2]};
|
q <= {q[length-1],q[0:length-2]};
|
endmodule
|
endmodule
|
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
|
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
|
parameter length = 4;
|
parameter length = 4;
|
input cke, clear;
|
input cke, clear;
|
output reg [0:length-1] q;
|
output reg [0:length-1] q;
|
input rst;
|
input rst;
|
input clk;
|
input clk;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
q <= {1'b1,{length-1{1'b0}}};
|
q <= {1'b1,{length-1{1'b0}}};
|
else
|
else
|
if (cke)
|
if (cke)
|
if (clear)
|
if (clear)
|
q <= {1'b1,{length-1{1'b0}}};
|
q <= {1'b1,{length-1{1'b0}}};
|
else
|
else
|
q <= q >> 1;
|
q <= q >> 1;
|
endmodule
|
endmodule
|
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
|
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
|
parameter length = 4;
|
parameter length = 4;
|
input cke, clear;
|
input cke, clear;
|
output reg [0:length-1] q;
|
output reg [0:length-1] q;
|
input rst;
|
input rst;
|
input clk;
|
input clk;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
q <= {1'b1,{length-1{1'b0}}};
|
q <= {1'b1,{length-1{1'b0}}};
|
else
|
else
|
if (cke)
|
if (cke)
|
if (clear)
|
if (clear)
|
q <= {1'b1,{length-1{1'b0}}};
|
q <= {1'b1,{length-1{1'b0}}};
|
else
|
else
|
q <= {q[length-1],q[0:length-2]};
|
q <= {q[length-1],q[0:length-2]};
|
endmodule
|
endmodule
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Versatile library, memories ////
|
//// Versatile library, memories ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
//// memories ////
|
//// memories ////
|
//// ////
|
//// ////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
//// - add more memory types ////
|
//// - add more memory types ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// ORSoC AB ////
|
//// ORSoC AB ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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/// ROM
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/// ROM
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module vl_rom_init ( adr, q, clk);
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module vl_rom_init ( adr, q, clk);
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parameter data_width = 32;
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parameter data_width = 32;
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parameter addr_width = 8;
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parameter addr_width = 8;
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input [(addr_width-1):0] adr;
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input [(addr_width-1):0] adr;
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output reg [(data_width-1):0] q;
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output reg [(data_width-1):0] q;
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input clk;
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input clk;
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reg [data_width-1:0] rom [(1<<addr_width)-1:0];
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reg [data_width-1:0] rom [(1<<addr_width)-1:0];
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parameter memory_file = "vl_rom.vmem";
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parameter memory_file = "vl_rom.vmem";
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initial
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initial
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begin
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begin
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$readmemh(memory_file, rom);
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$readmemh(memory_file, rom);
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end
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end
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always @ (posedge clk)
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always @ (posedge clk)
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q <= rom[adr];
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q <= rom[adr];
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endmodule
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endmodule
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/*
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/*
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module vl_rom ( adr, q, clk);
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module vl_rom ( adr, q, clk);
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parameter data_width = 32;
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parameter data_width = 32;
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parameter addr_width = 4;
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parameter addr_width = 4;
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parameter [0:1>>addr_width-1] data [data_width-1:0] = {
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parameter [0:1>>addr_width-1] data [data_width-1:0] = {
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{32'h18000000},
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{32'h18000000},
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{32'hA8200000},
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{32'hA8200000},
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{32'hA8200000},
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{32'hA8200000},
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{32'hA8200000},
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{32'hA8200000},
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{32'h44003000},
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{32'h44003000},
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{32'h15000000},
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{32'h15000000},
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{32'h15000000},
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{32'h15000000},
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{32'h15000000},
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{32'h15000000},
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{32'h15000000},
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{32'h15000000},
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{32'h15000000},
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{32'h15000000},
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{32'h15000000},
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{32'h15000000},
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{32'h15000000},
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{32'h15000000},
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{32'h15000000},
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{32'h15000000},
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{32'h15000000},
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{32'h15000000},
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{32'h15000000},
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{32'h15000000},
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{32'h15000000}};
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{32'h15000000}};
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input [addr_width-1:0] adr;
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input [addr_width-1:0] adr;
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output reg [data_width-1:0] q;
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output reg [data_width-1:0] q;
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input clk;
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input clk;
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always @ (posedge clk)
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always @ (posedge clk)
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q <= data[adr];
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q <= data[adr];
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endmodule
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endmodule
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*/
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*/
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// Single port RAM
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// Single port RAM
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module vl_ram ( d, adr, we, q, clk);
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module vl_ram ( d, adr, we, q, clk);
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parameter data_width = 32;
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parameter data_width = 32;
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parameter addr_width = 8;
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parameter addr_width = 8;
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input [(data_width-1):0] d;
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input [(data_width-1):0] d;
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input [(addr_width-1):0] adr;
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input [(addr_width-1):0] adr;
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input we;
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input we;
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output reg [(data_width-1):0] q;
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output reg [(data_width-1):0] q;
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input clk;
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input clk;
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reg [data_width-1:0] ram [(1<<addr_width)-1:0];
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reg [data_width-1:0] ram [(1<<addr_width)-1:0];
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parameter init = 0;
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parameter init = 0;
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parameter memory_file = "vl_ram.vmem";
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parameter memory_file = "vl_ram.vmem";
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generate if (init) begin : init_mem
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generate if (init) begin : init_mem
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initial
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initial
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begin
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begin
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$readmemh(memory_file, ram);
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$readmemh(memory_file, ram);
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end
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end
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end
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end
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endgenerate
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endgenerate
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always @ (posedge clk)
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always @ (posedge clk)
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begin
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begin
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if (we)
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if (we)
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ram[adr] <= d;
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ram[adr] <= d;
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q <= ram[adr];
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q <= ram[adr];
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end
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end
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endmodule
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endmodule
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module vl_ram_be ( d, adr, be, we, q, clk);
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module vl_ram_be ( d, adr, be, we, q, clk);
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parameter data_width = 32;
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parameter data_width = 32;
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parameter addr_width = 8;
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parameter addr_width = 8;
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input [(data_width-1):0] d;
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input [(data_width-1):0] d;
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input [(addr_width-1):0] adr;
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input [(addr_width-1):0] adr;
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input [(addr_width/4)-1:0] be;
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input [(addr_width/4)-1:0] be;
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input we;
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input we;
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output reg [(data_width-1):0] q;
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output reg [(data_width-1):0] q;
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input clk;
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input clk;
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reg [data_width-1:0] ram [(1<<addr_width)-1:0];
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reg [data_width-1:0] ram [(1<<addr_width)-1:0];
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parameter init = 0;
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parameter init = 0;
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parameter memory_file = "vl_ram.vmem";
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parameter memory_file = "vl_ram.vmem";
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generate if (init) begin : init_mem
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generate if (init) begin : init_mem
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initial
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initial
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begin
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begin
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$readmemh(memory_file, ram);
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$readmemh(memory_file, ram);
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end
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end
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end
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end
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endgenerate
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endgenerate
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genvar i;
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genvar i;
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generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
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generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
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always @ (posedge clk)
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always @ (posedge clk)
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if (we & be[i])
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if (we & be[i])
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ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
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ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
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end
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end
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endgenerate
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endgenerate
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always @ (posedge clk)
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always @ (posedge clk)
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q <= ram[adr];
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q <= ram[adr];
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endmodule
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endmodule
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// Dual port RAM
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// Dual port RAM
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// ACTEL FPGA should not use logic to handle rw collision
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// ACTEL FPGA should not use logic to handle rw collision
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module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
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module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
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parameter data_width = 32;
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parameter data_width = 32;
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parameter addr_width = 8;
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parameter addr_width = 8;
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input [(data_width-1):0] d_a;
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input [(data_width-1):0] d_a;
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input [(addr_width-1):0] adr_a;
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input [(addr_width-1):0] adr_a;
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input [(addr_width-1):0] adr_b;
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input [(addr_width-1):0] adr_b;
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input we_a;
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input we_a;
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output [(data_width-1):0] q_b;
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output [(data_width-1):0] q_b;
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input clk_a, clk_b;
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input clk_a, clk_b;
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reg [(addr_width-1):0] adr_b_reg;
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reg [(addr_width-1):0] adr_b_reg;
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reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
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reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
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parameter init = 0;
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parameter init = 0;
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parameter memory_file = "vl_ram.vmem";
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parameter memory_file = "vl_ram.vmem";
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generate if (init) begin : init_mem
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generate if (init) begin : init_mem
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initial
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initial
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begin
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begin
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$readmemh(memory_file, ram);
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$readmemh(memory_file, ram);
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end
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end
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end
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end
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endgenerate
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endgenerate
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always @ (posedge clk_a)
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always @ (posedge clk_a)
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if (we_a)
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if (we_a)
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ram[adr_a] <= d_a;
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ram[adr_a] <= d_a;
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always @ (posedge clk_b)
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always @ (posedge clk_b)
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adr_b_reg <= adr_b;
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adr_b_reg <= adr_b;
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assign q_b = ram[adr_b_reg];
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assign q_b = ram[adr_b_reg];
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endmodule
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endmodule
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module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
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module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
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parameter data_width = 32;
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parameter data_width = 32;
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parameter addr_width = 8;
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parameter addr_width = 8;
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input [(data_width-1):0] d_a;
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input [(data_width-1):0] d_a;
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input [(addr_width-1):0] adr_a;
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input [(addr_width-1):0] adr_a;
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input [(addr_width-1):0] adr_b;
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input [(addr_width-1):0] adr_b;
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input we_a;
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input we_a;
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output [(data_width-1):0] q_b;
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output [(data_width-1):0] q_b;
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output reg [(data_width-1):0] q_a;
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output reg [(data_width-1):0] q_a;
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input clk_a, clk_b;
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input clk_a, clk_b;
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reg [(data_width-1):0] q_b;
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reg [(data_width-1):0] q_b;
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reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
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reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
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parameter init = 0;
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parameter init = 0;
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parameter memory_file = "vl_ram.vmem";
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parameter memory_file = "vl_ram.vmem";
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generate if (init) begin : init_mem
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generate if (init) begin : init_mem
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initial
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initial
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begin
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begin
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$readmemh(memory_file, ram);
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$readmemh(memory_file, ram);
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end
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end
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end
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end
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endgenerate
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endgenerate
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always @ (posedge clk_a)
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always @ (posedge clk_a)
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begin
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begin
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q_a <= ram[adr_a];
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q_a <= ram[adr_a];
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if (we_a)
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if (we_a)
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ram[adr_a] <= d_a;
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ram[adr_a] <= d_a;
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end
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end
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always @ (posedge clk_b)
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always @ (posedge clk_b)
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q_b <= ram[adr_b];
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q_b <= ram[adr_b];
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endmodule
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endmodule
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module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
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module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
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parameter data_width = 32;
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parameter data_width = 32;
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parameter addr_width = 8;
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parameter addr_width = 8;
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input [(data_width-1):0] d_a;
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input [(data_width-1):0] d_a;
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input [(addr_width-1):0] adr_a;
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input [(addr_width-1):0] adr_a;
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input [(addr_width-1):0] adr_b;
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input [(addr_width-1):0] adr_b;
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input we_a;
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input we_a;
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output [(data_width-1):0] q_b;
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output [(data_width-1):0] q_b;
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input [(data_width-1):0] d_b;
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input [(data_width-1):0] d_b;
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output reg [(data_width-1):0] q_a;
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output reg [(data_width-1):0] q_a;
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input we_b;
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input we_b;
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input clk_a, clk_b;
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input clk_a, clk_b;
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reg [(data_width-1):0] q_b;
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reg [(data_width-1):0] q_b;
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reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
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reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
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parameter init = 0;
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parameter init = 0;
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parameter memory_file = "vl_ram.vmem";
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parameter memory_file = "vl_ram.vmem";
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generate if (init) begin : init_mem
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generate if (init) begin : init_mem
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initial
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initial
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begin
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begin
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$readmemh(memory_file, ram);
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$readmemh(memory_file, ram);
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end
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end
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end
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end
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endgenerate
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endgenerate
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always @ (posedge clk_a)
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always @ (posedge clk_a)
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begin
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begin
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q_a <= ram[adr_a];
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q_a <= ram[adr_a];
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if (we_a)
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if (we_a)
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ram[adr_a] <= d_a;
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ram[adr_a] <= d_a;
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end
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end
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always @ (posedge clk_b)
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always @ (posedge clk_b)
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begin
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begin
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q_b <= ram[adr_b];
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q_b <= ram[adr_b];
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if (we_b)
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if (we_b)
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ram[adr_b] <= d_b;
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ram[adr_b] <= d_b;
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end
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end
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endmodule
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endmodule
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// Content addresable memory, CAM
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// Content addresable memory, CAM
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// FIFO
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// FIFO
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module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
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module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
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parameter addr_width = 4;
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parameter addr_width = 4;
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parameter N = addr_width-1;
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parameter N = addr_width-1;
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parameter Q1 = 2'b00;
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parameter Q1 = 2'b00;
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parameter Q2 = 2'b01;
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parameter Q2 = 2'b01;
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parameter Q3 = 2'b11;
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parameter Q3 = 2'b11;
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parameter Q4 = 2'b10;
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parameter Q4 = 2'b10;
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parameter going_empty = 1'b0;
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parameter going_empty = 1'b0;
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parameter going_full = 1'b1;
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parameter going_full = 1'b1;
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input [N:0] wptr, rptr;
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input [N:0] wptr, rptr;
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output fifo_empty;
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output fifo_empty;
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output fifo_full;
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output fifo_full;
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input wclk, rclk, rst;
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input wclk, rclk, rst;
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wire direction;
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wire direction;
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reg direction_set, direction_clr;
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reg direction_set, direction_clr;
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wire async_empty, async_full;
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wire async_empty, async_full;
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wire fifo_full2;
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wire fifo_full2;
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wire fifo_empty2;
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wire fifo_empty2;
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// direction_set
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// direction_set
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always @ (wptr[N:N-1] or rptr[N:N-1])
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always @ (wptr[N:N-1] or rptr[N:N-1])
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case ({wptr[N:N-1],rptr[N:N-1]})
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case ({wptr[N:N-1],rptr[N:N-1]})
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{Q1,Q2} : direction_set <= 1'b1;
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{Q1,Q2} : direction_set <= 1'b1;
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{Q2,Q3} : direction_set <= 1'b1;
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{Q2,Q3} : direction_set <= 1'b1;
|
{Q3,Q4} : direction_set <= 1'b1;
|
{Q3,Q4} : direction_set <= 1'b1;
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{Q4,Q1} : direction_set <= 1'b1;
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{Q4,Q1} : direction_set <= 1'b1;
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default : direction_set <= 1'b0;
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default : direction_set <= 1'b0;
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endcase
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endcase
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// direction_clear
|
// direction_clear
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always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
|
always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
|
if (rst)
|
if (rst)
|
direction_clr <= 1'b1;
|
direction_clr <= 1'b1;
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else
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else
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case ({wptr[N:N-1],rptr[N:N-1]})
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case ({wptr[N:N-1],rptr[N:N-1]})
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{Q2,Q1} : direction_clr <= 1'b1;
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{Q2,Q1} : direction_clr <= 1'b1;
|
{Q3,Q2} : direction_clr <= 1'b1;
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{Q3,Q2} : direction_clr <= 1'b1;
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{Q4,Q3} : direction_clr <= 1'b1;
|
{Q4,Q3} : direction_clr <= 1'b1;
|
{Q1,Q4} : direction_clr <= 1'b1;
|
{Q1,Q4} : direction_clr <= 1'b1;
|
default : direction_clr <= 1'b0;
|
default : direction_clr <= 1'b0;
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endcase
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endcase
|
vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
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vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
|
assign async_empty = (wptr == rptr) && (direction==going_empty);
|
assign async_empty = (wptr == rptr) && (direction==going_empty);
|
assign async_full = (wptr == rptr) && (direction==going_full);
|
assign async_full = (wptr == rptr) && (direction==going_full);
|
vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
|
vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
|
vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
|
vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
|
/*
|
/*
|
always @ (posedge wclk or posedge rst or posedge async_full)
|
always @ (posedge wclk or posedge rst or posedge async_full)
|
if (rst)
|
if (rst)
|
{fifo_full, fifo_full2} <= 2'b00;
|
{fifo_full, fifo_full2} <= 2'b00;
|
else if (async_full)
|
else if (async_full)
|
{fifo_full, fifo_full2} <= 2'b11;
|
{fifo_full, fifo_full2} <= 2'b11;
|
else
|
else
|
{fifo_full, fifo_full2} <= {fifo_full2, async_full};
|
{fifo_full, fifo_full2} <= {fifo_full2, async_full};
|
*/
|
*/
|
/* always @ (posedge rclk or posedge async_empty)
|
/* always @ (posedge rclk or posedge async_empty)
|
if (async_empty)
|
if (async_empty)
|
{fifo_empty, fifo_empty2} <= 2'b11;
|
{fifo_empty, fifo_empty2} <= 2'b11;
|
else
|
else
|
{fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
|
{fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
|
vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
|
vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
|
vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty), .clk(rclk), .rst(async_empty));
|
vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty), .clk(rclk), .rst(async_empty));
|
endmodule // async_comp
|
endmodule // async_comp
|
module vl_fifo_1r1w_async (
|
module vl_fifo_1r1w_async (
|
d, wr, fifo_full, wr_clk, wr_rst,
|
d, wr, fifo_full, wr_clk, wr_rst,
|
q, rd, fifo_empty, rd_clk, rd_rst
|
q, rd, fifo_empty, rd_clk, rd_rst
|
);
|
);
|
parameter data_width = 18;
|
parameter data_width = 18;
|
parameter addr_width = 4;
|
parameter addr_width = 4;
|
// write side
|
// write side
|
input [data_width-1:0] d;
|
input [data_width-1:0] d;
|
input wr;
|
input wr;
|
output fifo_full;
|
output fifo_full;
|
input wr_clk;
|
input wr_clk;
|
input wr_rst;
|
input wr_rst;
|
// read side
|
// read side
|
output [data_width-1:0] q;
|
output [data_width-1:0] q;
|
input rd;
|
input rd;
|
output fifo_empty;
|
output fifo_empty;
|
input rd_clk;
|
input rd_clk;
|
input rd_rst;
|
input rd_rst;
|
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
|
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
|
vl_fifo_1r1w_async (
|
/*
|
d, wr, fifo_full, wr_clk, wr_rst,
|
vl_fifo_1r1w_async (
|
q, rd, fifo_empty, rd_clk, rd_rst
|
d, wr, fifo_full, wr_clk, wr_rst,
|
);
|
q, rd, fifo_empty, rd_clk, rd_rst
|
|
);
|
|
*/
|
vl_cnt_gray_ce_bin
|
vl_cnt_gray_ce_bin
|
# ( .length(addr_width))
|
# ( .length(addr_width))
|
fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
|
fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
|
vl_cnt_gray_ce_bin
|
vl_cnt_gray_ce_bin
|
# (.length(addr_width))
|
# (.length(addr_width))
|
fifo_rd_adr( .cke(wr), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_rst));
|
fifo_rd_adr( .cke(wr), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_rst));
|
vl_dpram_1r1w
|
vl_dpram_1r1w
|
# (.data_width(data_width), .addr_width(addr_width))
|
# (.data_width(data_width), .addr_width(addr_width))
|
dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
|
dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
|
vl_fifo_cmp_async
|
vl_fifo_cmp_async
|
# (.addr_width(addr_width))
|
# (.addr_width(addr_width))
|
cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
|
cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
|
endmodule
|
endmodule
|
module vl_fifo_2r2w_async (
|
module vl_fifo_2r2w_async (
|
// a side
|
// a side
|
a_d, a_wr, a_fifo_full,
|
a_d, a_wr, a_fifo_full,
|
a_q, a_rd, a_fifo_empty,
|
a_q, a_rd, a_fifo_empty,
|
a_clk, a_rst,
|
a_clk, a_rst,
|
// b side
|
// b side
|
b_d, b_wr, b_fifo_full,
|
b_d, b_wr, b_fifo_full,
|
b_q, b_rd, b_fifo_empty,
|
b_q, b_rd, b_fifo_empty,
|
b_clk, b_rst
|
b_clk, b_rst
|
);
|
);
|
parameter data_width = 18;
|
parameter data_width = 18;
|
parameter addr_width = 4;
|
parameter addr_width = 4;
|
// a side
|
// a side
|
input [data_width-1:0] a_d;
|
input [data_width-1:0] a_d;
|
input a_wr;
|
input a_wr;
|
output a_fifo_full;
|
output a_fifo_full;
|
output [data_width-1:0] a_q;
|
output [data_width-1:0] a_q;
|
input a_rd;
|
input a_rd;
|
output a_fifo_empty;
|
output a_fifo_empty;
|
input a_clk;
|
input a_clk;
|
input a_rst;
|
input a_rst;
|
// b side
|
// b side
|
input [data_width-1:0] b_d;
|
input [data_width-1:0] b_d;
|
input b_wr;
|
input b_wr;
|
output b_fifo_full;
|
output b_fifo_full;
|
output [data_width-1:0] b_q;
|
output [data_width-1:0] b_q;
|
input b_rd;
|
input b_rd;
|
output b_fifo_empty;
|
output b_fifo_empty;
|
input b_clk;
|
input b_clk;
|
input b_rst;
|
input b_rst;
|
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
|
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
|
vl_fifo_1r1w_async_a (
|
vl_fifo_1r1w_async_a (
|
.d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
|
.d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
|
.q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
|
.q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
|
);
|
);
|
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
|
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
|
vl_fifo_1r1w_async_b (
|
vl_fifo_1r1w_async_b (
|
.d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
|
.d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
|
.q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
|
.q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
|
);
|
);
|
endmodule
|
endmodule
|
module vl_fifo_2r2w_async_simplex (
|
module vl_fifo_2r2w_async_simplex (
|
// a side
|
// a side
|
a_d, a_wr, a_fifo_full,
|
a_d, a_wr, a_fifo_full,
|
a_q, a_rd, a_fifo_empty,
|
a_q, a_rd, a_fifo_empty,
|
a_clk, a_rst,
|
a_clk, a_rst,
|
// b side
|
// b side
|
b_d, b_wr, b_fifo_full,
|
b_d, b_wr, b_fifo_full,
|
b_q, b_rd, b_fifo_empty,
|
b_q, b_rd, b_fifo_empty,
|
b_clk, b_rst
|
b_clk, b_rst
|
);
|
)
|
