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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Diff between revs 23 and 24

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Rev 23 Rev 24
Line 163... Line 163...
                if (clear)
                if (clear)
                    q <= {width{1'b0}};
                    q <= {width{1'b0}};
                else
                else
                    q <= d;
                    q <= d;
endmodule
endmodule
 
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
 
        parameter width = 1;
 
        parameter reset_value = 0;
 
        input [width-1:0] d;
 
        input ce, set, clk, rst;
 
        output reg [width-1:0] q;
 
        always @ (posedge clk or posedge rst)
 
        if (rst)
 
            q <= reset_value;
 
        else
 
            if (ce)
 
                if (set)
 
                    q <= {width{1'b1}};
 
                else
 
                    q <= d;
 
endmodule
// megafunction wizard: %LPM_FF%
// megafunction wizard: %LPM_FF%
// GENERATION: STANDARD
// GENERATION: STANDARD
// VERSION: WM1.0
// VERSION: WM1.0
// MODULE: lpm_ff 
// MODULE: lpm_ff 
// ============================================================
// ============================================================

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