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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Diff between revs 44 and 45

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Rev 44 Rev 45
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//// You should have received a copy of the GNU Lesser General    ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
`timescale 1ns/1ns
module vl_o_dff (d_i, o_pad, clk, rst);
module vl_o_dff (d_i, o_pad, clk, rst);
parameter width = 1;
parameter width = 1;
 
parameter reset_value = {width{1'b0}};
input [width-1:0]  d_i;
input [width-1:0]  d_i;
output [width-1:0] o_pad;
output [width-1:0] o_pad;
input clk, rst;
input clk, rst;
wire [width-1:0] d_i_int `SYN_KEEP;
wire [width-1:0] d_i_int `SYN_KEEP;
 
reg  [width-1:0] o_pad_int;
assign d_i_int = d_i;
assign d_i_int = d_i;
genvar i;
genvar i;
 
generate
for (i=0;i<width;i=i+1) begin
for (i=0;i<width;i=i+1) begin
    always @ (posedge clk or posedge rst)
    always @ (posedge clk or posedge rst)
    if (rst)
    if (rst)
        o_pad[i] <= 1'b0;
        o_pad_int[i] <= reset_value[i];
    else
    else
        o_pad[i] <= d_i_int[i];
        o_pad_int[i] <= d_i_int[i];
 
    assign #1 o_pad[i] = o_pad_int[i];
end
end
endgenerate
endgenerate
endmodule
endmodule
 
`timescale 1ns/1ns
module vl_io_dff_oe ( d_i, d_o, oe, io_pad, clk, rst);
module vl_io_dff_oe ( d_i, d_o, oe, io_pad, clk, rst);
parameter width = 1;
parameter width = 1;
input  [width-1:0] d_o;
input  [width-1:0] d_o;
output reg [width-1:0] d_i;
output reg [width-1:0] d_i;
input oe;
input oe;
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    always @ (posedge clk or posedge rst)
    always @ (posedge clk or posedge rst)
    if (rst)
    if (rst)
        d_i[i] <= 1'b0;
        d_i[i] <= 1'b0;
    else
    else
        d_i[i] <= io_pad[i];
        d_i[i] <= io_pad[i];
    assign io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
end
end
endgenerate
endgenerate
endmodule
endmodule
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////

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