// default SYN_KEEP definition
|
// default SYN_KEEP definition
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Versatile library, clock and reset ////
|
//// Versatile library, clock and reset ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
//// Logic related to clock and reset ////
|
//// Logic related to clock and reset ////
|
//// ////
|
//// ////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
//// - add more different registers ////
|
//// - add more different registers ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// ORSoC AB ////
|
//// ORSoC AB ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//altera
|
//altera
|
module vl_gbuf ( i, o);
|
module vl_gbuf ( i, o);
|
input i;
|
input i;
|
output o;
|
output o;
|
assign o = i;
|
assign o = i;
|
endmodule
|
endmodule
|
// ALTERA
|
// ALTERA
|
//ACTEL
|
//ACTEL
|
// sync reset
|
// sync reset
|
// input active lo async reset, normally from external reset generator and/or switch
|
// input active lo async reset, normally from external reset generator and/or switch
|
// output active high global reset sync with two DFFs
|
// output active high global reset sync with two DFFs
|
`timescale 1 ns/100 ps
|
`timescale 1 ns/100 ps
|
module vl_sync_rst ( rst_n_i, rst_o, clk);
|
module vl_sync_rst ( rst_n_i, rst_o, clk);
|
input rst_n_i, clk;
|
input rst_n_i, clk;
|
output rst_o;
|
output rst_o;
|
reg [1:0] tmp;
|
reg [1:0] tmp;
|
always @ (posedge clk or negedge rst_n_i)
|
always @ (posedge clk or negedge rst_n_i)
|
if (!rst_n_i)
|
if (!rst_n_i)
|
tmp <= 2'b11;
|
tmp <= 2'b11;
|
else
|
else
|
tmp <= {1'b0,tmp[1]};
|
tmp <= {1'b0,tmp[1]};
|
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
|
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
|
endmodule
|
endmodule
|
// vl_pll
|
// vl_pll
|
///////////////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////////////
|
`timescale 1 ps/1 ps
|
`timescale 1 ps/1 ps
|
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
|
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
|
parameter index = 0;
|
parameter index = 0;
|
parameter number_of_clk = 1;
|
parameter number_of_clk = 1;
|
parameter period_time_0 = 20000;
|
parameter period_time_0 = 20000;
|
parameter period_time_1 = 20000;
|
parameter period_time_1 = 20000;
|
parameter period_time_2 = 20000;
|
parameter period_time_2 = 20000;
|
parameter period_time_3 = 20000;
|
parameter period_time_3 = 20000;
|
parameter period_time_4 = 20000;
|
parameter period_time_4 = 20000;
|
parameter lock_delay = 2000000;
|
parameter lock_delay = 2000000;
|
input clk_i, rst_n_i;
|
input clk_i, rst_n_i;
|
output lock;
|
output lock;
|
output reg [0:number_of_clk-1] clk_o;
|
output reg [0:number_of_clk-1] clk_o;
|
output [0:number_of_clk-1] rst_o;
|
output [0:number_of_clk-1] rst_o;
|
`ifdef SIM_PLL
|
`ifdef SIM_PLL
|
always
|
always
|
#((period_time_0)/2) clk_o[0] <= (!rst_n_i) ? 0 : ~clk_o[0];
|
#((period_time_0)/2) clk_o[0] <= (!rst_n_i) ? 0 : ~clk_o[0];
|
generate if (number_of_clk > 1)
|
generate if (number_of_clk > 1)
|
always
|
always
|
#((period_time_1)/2) clk_o[1] <= (!rst_n_i) ? 0 : ~clk_o[1];
|
#((period_time_1)/2) clk_o[1] <= (!rst_n_i) ? 0 : ~clk_o[1];
|
endgenerate
|
endgenerate
|
generate if (number_of_clk > 2)
|
generate if (number_of_clk > 2)
|
always
|
always
|
#((period_time_2)/2) clk_o[2] <= (!rst_n_i) ? 0 : ~clk_o[2];
|
#((period_time_2)/2) clk_o[2] <= (!rst_n_i) ? 0 : ~clk_o[2];
|
endgenerate
|
endgenerate
|
generate if (number_of_clk > 3)
|
generate if (number_of_clk > 3)
|
always
|
always
|
#((period_time_3)/2) clk_o[3] <= (!rst_n_i) ? 0 : ~clk_o[3];
|
#((period_time_3)/2) clk_o[3] <= (!rst_n_i) ? 0 : ~clk_o[3];
|
endgenerate
|
endgenerate
|
generate if (number_of_clk > 4)
|
generate if (number_of_clk > 4)
|
always
|
always
|
#((period_time_4)/2) clk_o[4] <= (!rst_n_i) ? 0 : ~clk_o[4];
|
#((period_time_4)/2) clk_o[4] <= (!rst_n_i) ? 0 : ~clk_o[4];
|
endgenerate
|
endgenerate
|
genvar i;
|
genvar i;
|
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
|
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
|
vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
|
vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
|
end
|
end
|
endgenerate
|
endgenerate
|
//assign #lock_delay lock = rst_n_i;
|
//assign #lock_delay lock = rst_n_i;
|
assign lock = rst_n_i;
|
assign lock = rst_n_i;
|
endmodule
|
endmodule
|
`else
|
`else
|
`ifdef VL_PLL0
|
`ifdef VL_PLL0
|
`ifdef VL_PLL0_CLK1
|
`ifdef VL_PLL0_CLK1
|
pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
|
pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
|
`endif
|
`endif
|
`ifdef VL_PLL0_CLK2
|
`ifdef VL_PLL0_CLK2
|
pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
|
pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
|
`endif
|
`endif
|
`ifdef VL_PLL0_CLK3
|
`ifdef VL_PLL0_CLK3
|
pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
|
pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
|
`endif
|
`endif
|
`ifdef VL_PLL0_CLK4
|
`ifdef VL_PLL0_CLK4
|
pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
|
pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
|
`endif
|
`endif
|
`ifdef VL_PLL0_CLK5
|
`ifdef VL_PLL0_CLK5
|
pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
|
pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
|
`endif
|
`endif
|
`endif
|
`endif
|
`ifdef VL_PLL1
|
`ifdef VL_PLL1
|
`ifdef VL_PLL1_CLK1
|
`ifdef VL_PLL1_CLK1
|
pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
|
pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
|
`endif
|
`endif
|
`ifdef VL_PLL1_CLK2
|
`ifdef VL_PLL1_CLK2
|
pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
|
pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
|
`endif
|
`endif
|
`ifdef VL_PLL1_CLK3
|
`ifdef VL_PLL1_CLK3
|
pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
|
pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
|
`endif
|
`endif
|
`ifdef VL_PLL1_CLK4
|
`ifdef VL_PLL1_CLK4
|
pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
|
pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
|
`endif
|
`endif
|
`ifdef VL_PLL1_CLK5
|
`ifdef VL_PLL1_CLK5
|
pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
|
pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
|
`endif
|
`endif
|
`endif
|
`endif
|
`ifdef VL_PLL2
|
`ifdef VL_PLL2
|
`ifdef VL_PLL2_CLK1
|
`ifdef VL_PLL2_CLK1
|
pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
|
pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
|
`endif
|
`endif
|
`ifdef VL_PLL2_CLK2
|
`ifdef VL_PLL2_CLK2
|
pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
|
pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
|
`endif
|
`endif
|
`ifdef VL_PLL2_CLK3
|
`ifdef VL_PLL2_CLK3
|
pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
|
pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
|
`endif
|
`endif
|
`ifdef VL_PLL2_CLK4
|
`ifdef VL_PLL2_CLK4
|
pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
|
pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
|
`endif
|
`endif
|
`ifdef VL_PLL2_CLK5
|
`ifdef VL_PLL2_CLK5
|
pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
|
pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
|
`endif
|
`endif
|
`endif
|
`endif
|
`ifdef VL_PLL3
|
`ifdef VL_PLL3
|
`ifdef VL_PLL3_CLK1
|
`ifdef VL_PLL3_CLK1
|
pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
|
pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
|
`endif
|
`endif
|
`ifdef VL_PLL3_CLK2
|
`ifdef VL_PLL3_CLK2
|
pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
|
pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
|
`endif
|
`endif
|
`ifdef VL_PLL3_CLK3
|
`ifdef VL_PLL3_CLK3
|
pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
|
pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
|
`endif
|
`endif
|
`ifdef VL_PLL3_CLK4
|
`ifdef VL_PLL3_CLK4
|
pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
|
pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
|
`endif
|
`endif
|
`ifdef VL_PLL3_CLK5
|
`ifdef VL_PLL3_CLK5
|
pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
|
pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
|
`endif
|
`endif
|
`endif
|
`endif
|
genvar i;
|
genvar i;
|
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
|
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
|
vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
|
vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
|
end
|
end
|
endgenerate
|
endgenerate
|
endmodule
|
endmodule
|
`endif
|
`endif
|
///////////////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////////////
|
//altera
|
//altera
|
//actel
|
//actel
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Versatile library, registers ////
|
//// Versatile library, registers ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
//// Different type of registers ////
|
//// Different type of registers ////
|
//// ////
|
//// ////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
//// - add more different registers ////
|
//// - add more different registers ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// ORSoC AB ////
|
//// ORSoC AB ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
module vl_dff ( d, q, clk, rst);
|
module vl_dff ( d, q, clk, rst);
|
parameter width = 1;
|
parameter width = 1;
|
parameter reset_value = 0;
|
parameter reset_value = 0;
|
input [width-1:0] d;
|
input [width-1:0] d;
|
input clk, rst;
|
input clk, rst;
|
output reg [width-1:0] q;
|
output reg [width-1:0] q;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
q <= reset_value;
|
q <= reset_value;
|
else
|
else
|
q <= d;
|
q <= d;
|
endmodule
|
endmodule
|
module vl_dff_array ( d, q, clk, rst);
|
module vl_dff_array ( d, q, clk, rst);
|
parameter width = 1;
|
parameter width = 1;
|
parameter depth = 2;
|
parameter depth = 2;
|
parameter reset_value = 1'b0;
|
parameter reset_value = 1'b0;
|
input [width-1:0] d;
|
input [width-1:0] d;
|
input clk, rst;
|
input clk, rst;
|
output [width-1:0] q;
|
output [width-1:0] q;
|
reg [0:depth-1] q_tmp [width-1:0];
|
reg [0:depth-1] q_tmp [width-1:0];
|
integer i;
|
integer i;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst) begin
|
if (rst) begin
|
for (i=0;i<depth;i=i+1)
|
for (i=0;i<depth;i=i+1)
|
q_tmp[i] <= {width{reset_value}};
|
q_tmp[i] <= {width{reset_value}};
|
end else begin
|
end else begin
|
q_tmp[0] <= d;
|
q_tmp[0] <= d;
|
for (i=1;i<depth;i=i+1)
|
for (i=1;i<depth;i=i+1)
|
q_tmp[i] <= q_tmp[i-1];
|
q_tmp[i] <= q_tmp[i-1];
|
end
|
end
|
assign q = q_tmp[depth-1];
|
assign q = q_tmp[depth-1];
|
endmodule
|
endmodule
|
module vl_dff_ce ( d, ce, q, clk, rst);
|
module vl_dff_ce ( d, ce, q, clk, rst);
|
parameter width = 1;
|
parameter width = 1;
|
parameter reset_value = 0;
|
parameter reset_value = 0;
|
input [width-1:0] d;
|
input [width-1:0] d;
|
input ce, clk, rst;
|
input ce, clk, rst;
|
output reg [width-1:0] q;
|
output reg [width-1:0] q;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
q <= reset_value;
|
q <= reset_value;
|
else
|
else
|
if (ce)
|
if (ce)
|
q <= d;
|
q <= d;
|
endmodule
|
endmodule
|
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
|
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
|
parameter width = 1;
|
parameter width = 1;
|
parameter reset_value = 0;
|
parameter reset_value = 0;
|
input [width-1:0] d;
|
input [width-1:0] d;
|
input ce, clear, clk, rst;
|
input ce, clear, clk, rst;
|
output reg [width-1:0] q;
|
output reg [width-1:0] q;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
q <= reset_value;
|
q <= reset_value;
|
else
|
else
|
if (ce)
|
if (ce)
|
if (clear)
|
if (clear)
|
q <= {width{1'b0}};
|
q <= {width{1'b0}};
|
else
|
else
|
q <= d;
|
q <= d;
|
endmodule
|
endmodule
|
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
|
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
|
parameter width = 1;
|
parameter width = 1;
|
parameter reset_value = 0;
|
parameter reset_value = 0;
|
input [width-1:0] d;
|
input [width-1:0] d;
|
input ce, set, clk, rst;
|
input ce, set, clk, rst;
|
output reg [width-1:0] q;
|
output reg [width-1:0] q;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
q <= reset_value;
|
q <= reset_value;
|
else
|
else
|
if (ce)
|
if (ce)
|
if (set)
|
if (set)
|
q <= {width{1'b1}};
|
q <= {width{1'b1}};
|
else
|
else
|
q <= d;
|
q <= d;
|
endmodule
|
endmodule
|
module vl_spr ( sp, r, q, clk, rst);
|
module vl_spr ( sp, r, q, clk, rst);
|
//parameter width = 1;
|
//parameter width = 1;
|
parameter reset_value = 1'b0;
|
parameter reset_value = 1'b0;
|
input sp, r;
|
input sp, r;
|
output reg q;
|
output reg q;
|
input clk, rst;
|
input clk, rst;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
q <= reset_value;
|
q <= reset_value;
|
else
|
else
|
if (sp)
|
if (sp)
|
q <= 1'b1;
|
q <= 1'b1;
|
else if (r)
|
else if (r)
|
q <= 1'b0;
|
q <= 1'b0;
|
endmodule
|
endmodule
|
module vl_srp ( s, rp, q, clk, rst);
|
module vl_srp ( s, rp, q, clk, rst);
|
parameter width = 1;
|
parameter width = 1;
|
parameter reset_value = 0;
|
parameter reset_value = 0;
|
input s, rp;
|
input s, rp;
|
output reg q;
|
output reg q;
|
input clk, rst;
|
input clk, rst;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
q <= reset_value;
|
q <= reset_value;
|
else
|
else
|
if (rp)
|
if (rp)
|
q <= 1'b0;
|
q <= 1'b0;
|
else if (s)
|
else if (s)
|
q <= 1'b1;
|
q <= 1'b1;
|
endmodule
|
endmodule
|
// megafunction wizard: %LPM_FF%
|
// megafunction wizard: %LPM_FF%
|
// GENERATION: STANDARD
|
// GENERATION: STANDARD
|
// VERSION: WM1.0
|
// VERSION: WM1.0
|
// MODULE: lpm_ff
|
// MODULE: lpm_ff
|
// ============================================================
|
// ============================================================
|
// File Name: dff_sr.v
|
// File Name: dff_sr.v
|
// Megafunction Name(s):
|
// Megafunction Name(s):
|
// lpm_ff
|
// lpm_ff
|
//
|
//
|
// Simulation Library Files(s):
|
// Simulation Library Files(s):
|
// lpm
|
// lpm
|
// ============================================================
|
// ============================================================
|
// ************************************************************
|
// ************************************************************
|
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
//
|
//
|
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
|
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
|
// ************************************************************
|
// ************************************************************
|
//Copyright (C) 1991-2010 Altera Corporation
|
//Copyright (C) 1991-2010 Altera Corporation
|
//Your use of Altera Corporation's design tools, logic functions
|
//Your use of Altera Corporation's design tools, logic functions
|
//and other software and tools, and its AMPP partner logic
|
//and other software and tools, and its AMPP partner logic
|
//functions, and any output files from any of the foregoing
|
//functions, and any output files from any of the foregoing
|
//(including device programming or simulation files), and any
|
//(including device programming or simulation files), and any
|
//associated documentation or information are expressly subject
|
//associated documentation or information are expressly subject
|
//to the terms and conditions of the Altera Program License
|
//to the terms and conditions of the Altera Program License
|
//Subscription Agreement, Altera MegaCore Function License
|
//Subscription Agreement, Altera MegaCore Function License
|
//Agreement, or other applicable license agreement, including,
|
//Agreement, or other applicable license agreement, including,
|
//without limitation, that your use is for the sole purpose of
|
//without limitation, that your use is for the sole purpose of
|
//programming logic devices manufactured by Altera and sold by
|
//programming logic devices manufactured by Altera and sold by
|
//Altera or its authorized distributors. Please refer to the
|
//Altera or its authorized distributors. Please refer to the
|
//applicable agreement for further details.
|
//applicable agreement for further details.
|
// synopsys translate_off
|
// synopsys translate_off
|
`timescale 1 ps / 1 ps
|
`timescale 1 ps / 1 ps
|
// synopsys translate_on
|
// synopsys translate_on
|
module vl_dff_sr (
|
module vl_dff_sr (
|
aclr,
|
aclr,
|
aset,
|
aset,
|
clock,
|
clock,
|
data,
|
data,
|
q);
|
q);
|
input aclr;
|
input aclr;
|
input aset;
|
input aset;
|
input clock;
|
input clock;
|
input data;
|
input data;
|
output q;
|
output q;
|
wire [0:0] sub_wire0;
|
wire [0:0] sub_wire0;
|
wire [0:0] sub_wire1 = sub_wire0[0:0];
|
wire [0:0] sub_wire1 = sub_wire0[0:0];
|
wire q = sub_wire1;
|
wire q = sub_wire1;
|
wire sub_wire2 = data;
|
wire sub_wire2 = data;
|
wire sub_wire3 = sub_wire2;
|
wire sub_wire3 = sub_wire2;
|
lpm_ff lpm_ff_component (
|
lpm_ff lpm_ff_component (
|
.aclr (aclr),
|
.aclr (aclr),
|
.clock (clock),
|
.clock (clock),
|
.data (sub_wire3),
|
.data (sub_wire3),
|
.aset (aset),
|
.aset (aset),
|
.q (sub_wire0)
|
.q (sub_wire0)
|
// synopsys translate_off
|
// synopsys translate_off
|
,
|
,
|
.aload (),
|
.aload (),
|
.enable (),
|
.enable (),
|
.sclr (),
|
.sclr (),
|
.sload (),
|
.sload (),
|
.sset ()
|
.sset ()
|
// synopsys translate_on
|
// synopsys translate_on
|
);
|
);
|
defparam
|
defparam
|
lpm_ff_component.lpm_fftype = "DFF",
|
lpm_ff_component.lpm_fftype = "DFF",
|
lpm_ff_component.lpm_type = "LPM_FF",
|
lpm_ff_component.lpm_type = "LPM_FF",
|
lpm_ff_component.lpm_width = 1;
|
lpm_ff_component.lpm_width = 1;
|
endmodule
|
endmodule
|
// ============================================================
|
// ============================================================
|
// CNX file retrieval info
|
// CNX file retrieval info
|
// ============================================================
|
// ============================================================
|
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
|
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
|
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
|
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
|
// Retrieval info: PRIVATE: ASET NUMERIC "1"
|
// Retrieval info: PRIVATE: ASET NUMERIC "1"
|
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
|
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
|
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
|
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
|
// Retrieval info: PRIVATE: DFF NUMERIC "1"
|
// Retrieval info: PRIVATE: DFF NUMERIC "1"
|
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
|
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
|
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
|
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
|
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
|
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
|
// Retrieval info: PRIVATE: SSET NUMERIC "0"
|
// Retrieval info: PRIVATE: SSET NUMERIC "0"
|
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
|
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
|
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
|
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
|
// Retrieval info: PRIVATE: nBit NUMERIC "1"
|
// Retrieval info: PRIVATE: nBit NUMERIC "1"
|
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
|
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
|
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
|
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
|
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
|
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
|
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
|
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
|
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
|
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
|
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
|
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
|
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
|
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
|
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
|
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
|
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
|
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
|
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
|
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
|
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
|
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
|
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
|
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
|
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
|
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
|
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
|
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
|
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
|
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
|
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
|
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
|
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
|
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
|
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
|
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
|
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
|
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
|
// Retrieval info: LIB_FILE: lpm
|
// Retrieval info: LIB_FILE: lpm
|
// LATCH
|
// LATCH
|
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
|
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
|
module vl_latch ( d, le, q, clk);
|
module vl_latch ( d, le, q, clk);
|
input d, le;
|
input d, le;
|
output q;
|
output q;
|
input clk;
|
input clk;
|
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
|
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
|
endmodule
|
endmodule
|
module vl_shreg ( d, q, clk, rst);
|
module vl_shreg ( d, q, clk, rst);
|
parameter depth = 10;
|
parameter depth = 10;
|
input d;
|
input d;
|
output q;
|
output q;
|
input clk, rst;
|
input clk, rst;
|
reg [1:depth] dffs;
|
reg [1:depth] dffs;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
dffs <= {depth{1'b0}};
|
dffs <= {depth{1'b0}};
|
else
|
else
|
dffs <= {d,dffs[1:depth-1]};
|
dffs <= {d,dffs[1:depth-1]};
|
assign q = dffs[depth];
|
assign q = dffs[depth];
|
endmodule
|
endmodule
|
module vl_shreg_ce ( d, ce, q, clk, rst);
|
module vl_shreg_ce ( d, ce, q, clk, rst);
|
parameter depth = 10;
|
parameter depth = 10;
|
input d, ce;
|
input d, ce;
|
output q;
|
output q;
|
input clk, rst;
|
input clk, rst;
|
reg [1:depth] dffs;
|
reg [1:depth] dffs;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
dffs <= {depth{1'b0}};
|
dffs <= {depth{1'b0}};
|
else
|
else
|
if (ce)
|
if (ce)
|
dffs <= {d,dffs[1:depth-1]};
|
dffs <= {d,dffs[1:depth-1]};
|
assign q = dffs[depth];
|
assign q = dffs[depth];
|
endmodule
|
endmodule
|
module vl_delay ( d, q, clk, rst);
|
module vl_delay ( d, q, clk, rst);
|
parameter depth = 10;
|
parameter depth = 10;
|
input d;
|
input d;
|
output q;
|
output q;
|
input clk, rst;
|
input clk, rst;
|
reg [1:depth] dffs;
|
reg [1:depth] dffs;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
dffs <= {depth{1'b0}};
|
dffs <= {depth{1'b0}};
|
else
|
else
|
dffs <= {d,dffs[1:depth-1]};
|
dffs <= {d,dffs[1:depth-1]};
|
assign q = dffs[depth];
|
assign q = dffs[depth];
|
endmodule
|
endmodule
|
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
|
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
|
parameter depth = 10;
|
parameter depth = 10;
|
input d;
|
input d;
|
output q, emptyflag;
|
output q, emptyflag;
|
input clk, rst;
|
input clk, rst;
|
reg [1:depth] dffs;
|
reg [1:depth] dffs;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
dffs <= {depth{1'b0}};
|
dffs <= {depth{1'b0}};
|
else
|
else
|
dffs <= {d,dffs[1:depth-1]};
|
dffs <= {d,dffs[1:depth-1]};
|
assign q = dffs[depth];
|
assign q = dffs[depth];
|
assign emptyflag = !(|dffs);
|
assign emptyflag = !(|dffs);
|
endmodule
|
endmodule
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Logic functions ////
|
//// Logic functions ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
//// Logic functions such as multiplexers ////
|
//// Logic functions such as multiplexers ////
|
//// ////
|
//// ////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
//// - ////
|
//// - ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// ORSoC AB ////
|
//// ORSoC AB ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
module vl_mux_andor ( a, sel, dout);
|
module vl_mux_andor ( a, sel, dout);
|
parameter width = 32;
|
parameter width = 32;
|
parameter nr_of_ports = 4;
|
parameter nr_of_ports = 4;
|
input [nr_of_ports*width-1:0] a;
|
input [nr_of_ports*width-1:0] a;
|
input [nr_of_ports-1:0] sel;
|
input [nr_of_ports-1:0] sel;
|
output reg [width-1:0] dout;
|
output reg [width-1:0] dout;
|
integer i,j;
|
integer i,j;
|
always @ (a, sel)
|
always @ (a, sel)
|
begin
|
begin
|
dout = a[width-1:0] & {width{sel[0]}};
|
dout = a[width-1:0] & {width{sel[0]}};
|
for (i=1;i<nr_of_ports;i=i+1)
|
for (i=1;i<nr_of_ports;i=i+1)
|
for (j=0;j<width;j=j+1)
|
for (j=0;j<width;j=j+1)
|
dout[j] = (a[i*width + j] & sel[i]) | dout[j];
|
dout[j] = (a[i*width + j] & sel[i]) | dout[j];
|
end
|
end
|
endmodule
|
endmodule
|
module vl_mux2_andor ( a1, a0, sel, dout);
|
module vl_mux2_andor ( a1, a0, sel, dout);
|
parameter width = 32;
|
parameter width = 32;
|
localparam nr_of_ports = 2;
|
localparam nr_of_ports = 2;
|
input [width-1:0] a1, a0;
|
input [width-1:0] a1, a0;
|
input [nr_of_ports-1:0] sel;
|
input [nr_of_ports-1:0] sel;
|
output [width-1:0] dout;
|
output [width-1:0] dout;
|
vl_mux_andor
|
vl_mux_andor
|
# ( .width(width), .nr_of_ports(nr_of_ports))
|
# ( .width(width), .nr_of_ports(nr_of_ports))
|
mux0( .a({a1,a0}), .sel(sel), .dout(dout));
|
mux0( .a({a1,a0}), .sel(sel), .dout(dout));
|
endmodule
|
endmodule
|
module vl_mux3_andor ( a2, a1, a0, sel, dout);
|
module vl_mux3_andor ( a2, a1, a0, sel, dout);
|
parameter width = 32;
|
parameter width = 32;
|
localparam nr_of_ports = 3;
|
localparam nr_of_ports = 3;
|
input [width-1:0] a2, a1, a0;
|
input [width-1:0] a2, a1, a0;
|
input [nr_of_ports-1:0] sel;
|
input [nr_of_ports-1:0] sel;
|
output [width-1:0] dout;
|
output [width-1:0] dout;
|
vl_mux_andor
|
vl_mux_andor
|
# ( .width(width), .nr_of_ports(nr_of_ports))
|
# ( .width(width), .nr_of_ports(nr_of_ports))
|
mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
|
mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
|
endmodule
|
endmodule
|
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
|
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
|
parameter width = 32;
|
parameter width = 32;
|
localparam nr_of_ports = 4;
|
localparam nr_of_ports = 4;
|
input [width-1:0] a3, a2, a1, a0;
|
input [width-1:0] a3, a2, a1, a0;
|
input [nr_of_ports-1:0] sel;
|
input [nr_of_ports-1:0] sel;
|
output [width-1:0] dout;
|
output [width-1:0] dout;
|
vl_mux_andor
|
vl_mux_andor
|
# ( .width(width), .nr_of_ports(nr_of_ports))
|
# ( .width(width), .nr_of_ports(nr_of_ports))
|
mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
|
mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
|
endmodule
|
endmodule
|
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
|
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
|
parameter width = 32;
|
parameter width = 32;
|
localparam nr_of_ports = 5;
|
localparam nr_of_ports = 5;
|
input [width-1:0] a4, a3, a2, a1, a0;
|
input [width-1:0] a4, a3, a2, a1, a0;
|
input [nr_of_ports-1:0] sel;
|
input [nr_of_ports-1:0] sel;
|
output [width-1:0] dout;
|
output [width-1:0] dout;
|
vl_mux_andor
|
vl_mux_andor
|
# ( .width(width), .nr_of_ports(nr_of_ports))
|
# ( .width(width), .nr_of_ports(nr_of_ports))
|
mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
|
mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
|
endmodule
|
endmodule
|
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
|
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
|
parameter width = 32;
|
parameter width = 32;
|
localparam nr_of_ports = 6;
|
localparam nr_of_ports = 6;
|
input [width-1:0] a5, a4, a3, a2, a1, a0;
|
input [width-1:0] a5, a4, a3, a2, a1, a0;
|
input [nr_of_ports-1:0] sel;
|
input [nr_of_ports-1:0] sel;
|
output [width-1:0] dout;
|
output [width-1:0] dout;
|
vl_mux_andor
|
vl_mux_andor
|
# ( .width(width), .nr_of_ports(nr_of_ports))
|
# ( .width(width), .nr_of_ports(nr_of_ports))
|
mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
|
mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
|
endmodule
|
endmodule
|
module vl_parity_generate (data, parity);
|
module vl_parity_generate (data, parity);
|
parameter word_size = 32;
|
parameter word_size = 32;
|
parameter chunk_size = 8;
|
parameter chunk_size = 8;
|
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
|
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
|
input [word_size-1:0] data;
|
input [word_size-1:0] data;
|
output reg [word_size/chunk_size-1:0] parity;
|
output reg [word_size/chunk_size-1:0] parity;
|
integer i,j;
|
integer i,j;
|
always @ (data)
|
always @ (data)
|
for (i=0;i<word_size/chunk_size;i=i+1) begin
|
for (i=0;i<word_size/chunk_size;i=i+1) begin
|
parity[i] = parity_type;
|
parity[i] = parity_type;
|
for (j=0;j<chunk_size;j=j+1) begin
|
for (j=0;j<chunk_size;j=j+1) begin
|
parity[i] = data[i*chunk_size+j] ^ parity[i];
|
parity[i] = data[i*chunk_size+j] ^ parity[i];
|
end
|
end
|
end
|
end
|
endmodule
|
endmodule
|
module vl_parity_check( data, parity, parity_error);
|
module vl_parity_check( data, parity, parity_error);
|
parameter word_size = 32;
|
parameter word_size = 32;
|
parameter chunk_size = 8;
|
parameter chunk_size = 8;
|
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
|
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
|
input [word_size-1:0] data;
|
input [word_size-1:0] data;
|
input [word_size/chunk_size-1:0] parity;
|
input [word_size/chunk_size-1:0] parity;
|
output parity_error;
|
output parity_error;
|
reg [word_size/chunk_size-1:0] error_flag;
|
reg [word_size/chunk_size-1:0] error_flag;
|
integer i,j;
|
integer i,j;
|
always @ (data or parity)
|
always @ (data or parity)
|
for (i=0;i<word_size/chunk_size;i=i+1) begin
|
for (i=0;i<word_size/chunk_size;i=i+1) begin
|
error_flag[i] = parity[i] ^ parity_type;
|
error_flag[i] = parity[i] ^ parity_type;
|
for (j=0;j<chunk_size;j=j+1) begin
|
for (j=0;j<chunk_size;j=j+1) begin
|
error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
|
error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
|
end
|
end
|
end
|
end
|
assign parity_error = |error_flag;
|
assign parity_error = |error_flag;
|
endmodule
|
endmodule
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// IO functions ////
|
//// IO functions ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
//// IO functions such as IOB flip-flops ////
|
//// IO functions such as IOB flip-flops ////
|
//// ////
|
//// ////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
//// - ////
|
//// - ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// ORSoC AB ////
|
//// ORSoC AB ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
`timescale 1ns/1ns
|
`timescale 1ns/1ns
|
module vl_o_dff (d_i, o_pad, clk, rst);
|
module vl_o_dff (d_i, o_pad, clk, rst);
|
parameter width = 1;
|
parameter width = 1;
|
parameter reset_value = {width{1'b0}};
|
parameter reset_value = {width{1'b0}};
|
input [width-1:0] d_i;
|
input [width-1:0] d_i;
|
output [width-1:0] o_pad;
|
output [width-1:0] o_pad;
|
input clk, rst;
|
input clk, rst;
|
wire [width-1:0] d_i_int /*synthesis syn_keep = 1*/;
|
wire [width-1:0] d_i_int /*synthesis syn_keep = 1*/;
|
reg [width-1:0] o_pad_int;
|
reg [width-1:0] o_pad_int;
|
assign d_i_int = d_i;
|
assign d_i_int = d_i;
|
genvar i;
|
genvar i;
|
generate
|
generate
|
for (i=0;i<width;i=i+1) begin
|
for (i=0;i<width;i=i+1) begin
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
o_pad_int[i] <= reset_value[i];
|
o_pad_int[i] <= reset_value[i];
|
else
|
else
|
o_pad_int[i] <= d_i_int[i];
|
o_pad_int[i] <= d_i_int[i];
|
assign #1 o_pad[i] = o_pad_int[i];
|
assign #1 o_pad[i] = o_pad_int[i];
|
end
|
end
|
endgenerate
|
endgenerate
|
endmodule
|
endmodule
|
`timescale 1ns/1ns
|
`timescale 1ns/1ns
|
module vl_io_dff_oe ( d_i, d_o, oe, io_pad, clk, rst);
|
module vl_io_dff_oe ( d_i, d_o, oe, io_pad, clk, rst);
|
parameter width = 1;
|
parameter width = 1;
|
input [width-1:0] d_o;
|
input [width-1:0] d_o;
|
output reg [width-1:0] d_i;
|
output reg [width-1:0] d_i;
|
input oe;
|
input oe;
|
inout [width-1:0] io_pad;
|
inout [width-1:0] io_pad;
|
input clk, rst;
|
input clk, rst;
|
wire [width-1:0] oe_d /*synthesis syn_keep = 1*/;
|
wire [width-1:0] oe_d /*synthesis syn_keep = 1*/;
|
reg [width-1:0] oe_q;
|
reg [width-1:0] oe_q;
|
reg [width-1:0] d_o_q;
|
reg [width-1:0] d_o_q;
|
assign oe_d = {width{oe}};
|
assign oe_d = {width{oe}};
|
genvar i;
|
genvar i;
|
generate
|
generate
|
for (i=0;i<width;i=i+1) begin
|
for (i=0;i<width;i=i+1) begin
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
oe_q[i] <= 1'b0;
|
oe_q[i] <= 1'b0;
|
else
|
else
|
oe_q[i] <= oe_d[i];
|
oe_q[i] <= oe_d[i];
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
d_o_q[i] <= 1'b0;
|
d_o_q[i] <= 1'b0;
|
else
|
else
|
d_o_q[i] <= d_o[i];
|
d_o_q[i] <= d_o[i];
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
d_i[i] <= 1'b0;
|
d_i[i] <= 1'b0;
|
else
|
else
|
d_i[i] <= io_pad[i];
|
d_i[i] <= io_pad[i];
|
assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
|
assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
|
end
|
end
|
endgenerate
|
endgenerate
|
endmodule
|
endmodule
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Versatile counter ////
|
//// Versatile counter ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
//// counter ////
|
//// counter ////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
//// - add LFSR with more taps ////
|
//// - add LFSR with more taps ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// ORSoC AB ////
|
//// ORSoC AB ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
// binary counter
|
// binary counter
|
module vl_cnt_bin_ce (
|
module vl_cnt_bin_ce (
|
cke, q, rst, clk);
|
cke, q, rst, clk);
|
parameter length = 4;
|
parameter length = 4;
|
input cke;
|
input cke;
|
output [length:1] q;
|
output [length:1] q;
|
input rst;
|
input rst;
|
input clk;
|
input clk;
|
parameter clear_value = 0;
|
parameter clear_value = 0;
|
parameter set_value = 1;
|
parameter set_value = 1;
|
parameter wrap_value = 0;
|
parameter wrap_value = 0;
|
parameter level1_value = 15;
|
parameter level1_value = 15;
|
reg [length:1] qi;
|
reg [length:1] qi;
|
wire [length:1] q_next;
|
wire [length:1] q_next;
|
assign q_next = qi + {{length-1{1'b0}},1'b1};
|
assign q_next = qi + {{length-1{1'b0}},1'b1};
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
qi <= {length{1'b0}};
|
qi <= {length{1'b0}};
|
else
|
else
|
if (cke)
|
if (cke)
|
qi <= q_next;
|
qi <= q_next;
|
assign q = qi;
|
assign q = qi;
|
endmodule
|
endmodule
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Versatile counter ////
|
//// Versatile counter ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
//// counter ////
|
//// counter ////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
//// - add LFSR with more taps ////
|
//// - add LFSR with more taps ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// ORSoC AB ////
|
//// ORSoC AB ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
// binary counter
|
// binary counter
|
module vl_cnt_bin_ce_rew_zq_l1 (
|
module vl_cnt_bin_ce_rew_zq_l1 (
|
cke, rew, zq, level1, rst, clk);
|
cke, rew, zq, level1, rst, clk);
|
parameter length = 4;
|
parameter length = 4;
|
input cke;
|
input cke;
|
input rew;
|
input rew;
|
output reg zq;
|
output reg zq;
|
output reg level1;
|
output reg level1;
|
input rst;
|
input rst;
|
input clk;
|
input clk;
|
parameter clear_value = 0;
|
parameter clear_value = 0;
|
parameter set_value = 1;
|
parameter set_value = 1;
|
parameter wrap_value = 1;
|
parameter wrap_value = 1;
|
parameter level1_value = 15;
|
parameter level1_value = 15;
|
wire clear;
|
wire clear;
|
assign clear = 1'b0;
|
assign clear = 1'b0;
|
reg [length:1] qi;
|
reg [length:1] qi;
|
wire [length:1] q_next, q_next_fw, q_next_rew;
|
wire [length:1] q_next, q_next_fw, q_next_rew;
|
assign q_next_fw = qi + {{length-1{1'b0}},1'b1};
|
assign q_next_fw = qi + {{length-1{1'b0}},1'b1};
|
assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
|
assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
|
assign q_next = rew ? q_next_rew : q_next_fw;
|
assign q_next = rew ? q_next_rew : q_next_fw;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
qi <= {length{1'b0}};
|
qi <= {length{1'b0}};
|
else
|
else
|
if (cke)
|
if (cke)
|
qi <= q_next;
|
qi <= q_next;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
zq <= 1'b1;
|
zq <= 1'b1;
|
else
|
else
|
if (cke)
|
if (cke)
|
zq <= q_next == {length{1'b0}};
|
zq <= q_next == {length{1'b0}};
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
level1 <= 1'b0;
|
level1 <= 1'b0;
|
else
|
else
|
if (cke)
|
if (cke)
|
if (clear)
|
if (clear)
|
level1 <= 1'b0;
|
level1 <= 1'b0;
|
else if (q_next == level1_value)
|
else if (q_next == level1_value)
|
level1 <= 1'b1;
|
level1 <= 1'b1;
|
else if (qi == level1_value & rew)
|
else if (qi == level1_value & rew)
|
level1 <= 1'b0;
|
level1 <= 1'b0;
|
endmodule
|
endmodule
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Versatile counter ////
|
//// Versatile counter ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
//// counter ////
|
//// counter ////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
//// - add LFSR with more taps ////
|
//// - add LFSR with more taps ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// ORSoC AB ////
|
//// ORSoC AB ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
// binary counter
|
// binary counter
|
module vl_cnt_bin_ce_rew_q_zq_l1 (
|
module vl_cnt_bin_ce_rew_q_zq_l1 (
|
cke, rew, q, zq, level1, rst, clk);
|
cke, rew, q, zq, level1, rst, clk);
|
parameter length = 4;
|
parameter length = 4;
|
input cke;
|
input cke;
|
input rew;
|
input rew;
|
output [length:1] q;
|
output [length:1] q;
|
output reg zq;
|
output reg zq;
|
output reg level1;
|
output reg level1;
|
input rst;
|
input rst;
|
input clk;
|
input clk;
|
parameter clear_value = 0;
|
parameter clear_value = 0;
|
parameter set_value = 1;
|
parameter set_value = 1;
|
parameter wrap_value = 1;
|
parameter wrap_value = 1;
|
parameter level1_value = 15;
|
parameter level1_value = 15;
|
wire clear;
|
wire clear;
|
assign clear = 1'b0;
|
assign clear = 1'b0;
|
reg [length:1] qi;
|
reg [length:1] qi;
|
wire [length:1] q_next, q_next_fw, q_next_rew;
|
wire [length:1] q_next, q_next_fw, q_next_rew;
|
assign q_next_fw = qi + {{length-1{1'b0}},1'b1};
|
assign q_next_fw = qi + {{length-1{1'b0}},1'b1};
|
assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
|
assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
|
assign q_next = rew ? q_next_rew : q_next_fw;
|
assign q_next = rew ? q_next_rew : q_next_fw;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
qi <= {length{1'b0}};
|
qi <= {length{1'b0}};
|
else
|
else
|
if (cke)
|
if (cke)
|
qi <= q_next;
|
qi <= q_next;
|
assign q = qi;
|
assign q = qi;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
zq <= 1'b1;
|
zq <= 1'b1;
|
else
|
else
|
if (cke)
|
if (cke)
|
zq <= q_next == {length{1'b0}};
|
zq <= q_next == {length{1'b0}};
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
level1 <= 1'b0;
|
level1 <= 1'b0;
|
else
|
else
|
if (cke)
|
if (cke)
|
if (clear)
|
if (clear)
|
level1 <= 1'b0;
|
level1 <= 1'b0;
|
else if (q_next == level1_value)
|
else if (q_next == level1_value)
|
level1 <= 1'b1;
|
level1 <= 1'b1;
|
else if (qi == level1_value & rew)
|
else if (qi == level1_value & rew)
|
level1 <= 1'b0;
|
level1 <= 1'b0;
|
endmodule
|
endmodule
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Versatile counter ////
|
//// Versatile counter ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
//// counter ////
|
//// counter ////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
//// - add LFSR with more taps ////
|
//// - add LFSR with more taps ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// ORSoC AB ////
|
//// ORSoC AB ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
// GRAY counter
|
// GRAY counter
|
module vl_cnt_gray_ce_bin (
|
module vl_cnt_gray_ce_bin (
|
cke, q, q_bin, rst, clk);
|
cke, q, q_bin, rst, clk);
|
parameter length = 4;
|
parameter length = 4;
|
input cke;
|
input cke;
|
output reg [length:1] q;
|
output reg [length:1] q;
|
output [length:1] q_bin;
|
output [length:1] q_bin;
|
input rst;
|
input rst;
|
input clk;
|
input clk;
|
parameter clear_value = 0;
|
parameter clear_value = 0;
|
parameter set_value = 1;
|
parameter set_value = 1;
|
parameter wrap_value = 8;
|
parameter wrap_value = 8;
|
parameter level1_value = 15;
|
parameter level1_value = 15;
|
reg [length:1] qi;
|
reg [length:1] qi;
|
wire [length:1] q_next;
|
wire [length:1] q_next;
|
assign q_next = qi + {{length-1{1'b0}},1'b1};
|
assign q_next = qi + {{length-1{1'b0}},1'b1};
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
qi <= {length{1'b0}};
|
qi <= {length{1'b0}};
|
else
|
else
|
if (cke)
|
if (cke)
|
qi <= q_next;
|
qi <= q_next;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
q <= {length{1'b0}};
|
q <= {length{1'b0}};
|
else
|
else
|
if (cke)
|
if (cke)
|
q <= (q_next>>1) ^ q_next;
|
q <= (q_next>>1) ^ q_next;
|
assign q_bin = qi;
|
assign q_bin = qi;
|
endmodule
|
endmodule
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Versatile library, counters ////
|
//// Versatile library, counters ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
//// counters ////
|
//// counters ////
|
//// ////
|
//// ////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
//// - add more counters ////
|
//// - add more counters ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// ORSoC AB ////
|
//// ORSoC AB ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
module vl_cnt_shreg_wrap ( q, rst, clk);
|
module vl_cnt_shreg_wrap ( q, rst, clk);
|
parameter length = 4;
|
parameter length = 4;
|
output reg [0:length-1] q;
|
output reg [0:length-1] q;
|
input rst;
|
input rst;
|
input clk;
|
input clk;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
q <= {1'b1,{length-1{1'b0}}};
|
q <= {1'b1,{length-1{1'b0}}};
|
else
|
else
|
q <= {q[length-1],q[0:length-2]};
|
q <= {q[length-1],q[0:length-2]};
|
endmodule
|
endmodule
|
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
|
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
|
parameter length = 4;
|
parameter length = 4;
|
input cke;
|
input cke;
|
output reg [0:length-1] q;
|
output reg [0:length-1] q;
|
input rst;
|
input rst;
|
input clk;
|
input clk;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
q <= {1'b1,{length-1{1'b0}}};
|
q <= {1'b1,{length-1{1'b0}}};
|
else
|
else
|
if (cke)
|
if (cke)
|
q <= {q[length-1],q[0:length-2]};
|
q <= {q[length-1],q[0:length-2]};
|
endmodule
|
endmodule
|
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
|
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
|
parameter length = 4;
|
parameter length = 4;
|
input cke, clear;
|
input cke, clear;
|
output reg [0:length-1] q;
|
output reg [0:length-1] q;
|
input rst;
|
input rst;
|
input clk;
|
input clk;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
q <= {1'b1,{length-1{1'b0}}};
|
q <= {1'b1,{length-1{1'b0}}};
|
else
|
else
|
if (cke)
|
if (cke)
|
if (clear)
|
if (clear)
|
q <= {1'b1,{length-1{1'b0}}};
|
q <= {1'b1,{length-1{1'b0}}};
|
else
|
else
|
q <= q >> 1;
|
q <= q >> 1;
|
endmodule
|
endmodule
|
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
|
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
|
parameter length = 4;
|
parameter length = 4;
|
input cke, clear;
|
input cke, clear;
|
output reg [0:length-1] q;
|
output reg [0:length-1] q;
|
input rst;
|
input rst;
|
input clk;
|
input clk;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
q <= {1'b1,{length-1{1'b0}}};
|
q <= {1'b1,{length-1{1'b0}}};
|
else
|
else
|
if (cke)
|
if (cke)
|
if (clear)
|
if (clear)
|
q <= {1'b1,{length-1{1'b0}}};
|
q <= {1'b1,{length-1{1'b0}}};
|
else
|
else
|
q <= {q[length-1],q[0:length-2]};
|
q <= {q[length-1],q[0:length-2]};
|
endmodule
|
endmodule
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Versatile library, memories ////
|
//// Versatile library, memories ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
//// memories ////
|
//// memories ////
|
//// ////
|
//// ////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
//// - add more memory types ////
|
//// - add more memory types ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// ORSoC AB ////
|
//// ORSoC AB ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
/// ROM
|
/// ROM
|
module vl_rom_init ( adr, q, clk);
|
module vl_rom_init ( adr, q, clk);
|
parameter data_width = 32;
|
parameter data_width = 32;
|
parameter addr_width = 8;
|
parameter addr_width = 8;
|
input [(addr_width-1):0] adr;
|
input [(addr_width-1):0] adr;
|
output reg [(data_width-1):0] q;
|
output reg [(data_width-1):0] q;
|
input clk;
|
input clk;
|
reg [data_width-1:0] rom [(1<<addr_width)-1:0];
|
reg [data_width-1:0] rom [(1<<addr_width)-1:0];
|
parameter memory_file = "vl_rom.vmem";
|
parameter memory_file = "vl_rom.vmem";
|
initial
|
initial
|
begin
|
begin
|
$readmemh(memory_file, rom);
|
$readmemh(memory_file, rom);
|
end
|
end
|
always @ (posedge clk)
|
always @ (posedge clk)
|
q <= rom[adr];
|
q <= rom[adr];
|
endmodule
|
endmodule
|
// Single port RAM
|
// Single port RAM
|
module vl_ram ( d, adr, we, q, clk);
|
module vl_ram ( d, adr, we, q, clk);
|
parameter data_width = 32;
|
parameter data_width = 32;
|
parameter addr_width = 8;
|
parameter addr_width = 8;
|
input [(data_width-1):0] d;
|
input [(data_width-1):0] d;
|
input [(addr_width-1):0] adr;
|
input [(addr_width-1):0] adr;
|
input we;
|
input we;
|
output reg [(data_width-1):0] q;
|
output reg [(data_width-1):0] q;
|
input clk;
|
input clk;
|
reg [data_width-1:0] ram [(1<<addr_width)-1:0];
|
reg [data_width-1:0] ram [(1<<addr_width)-1:0];
|
parameter init = 0;
|
parameter init = 0;
|
parameter memory_file = "vl_ram.vmem";
|
parameter memory_file = "vl_ram.vmem";
|
generate if (init) begin : init_mem
|
generate if (init) begin : init_mem
|
initial
|
initial
|
begin
|
begin
|
$readmemh(memory_file, ram);
|
$readmemh(memory_file, ram);
|
end
|
end
|
end
|
end
|
endgenerate
|
endgenerate
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin
|
begin
|
if (we)
|
if (we)
|
ram[adr] <= d;
|
ram[adr] <= d;
|
q <= ram[adr];
|
q <= ram[adr];
|
end
|
end
|
endmodule
|
endmodule
|
module vl_ram_be ( d, adr, be, we, q, clk);
|
module vl_ram_be ( d, adr, be, we, q, clk);
|
parameter data_width = 32;
|
parameter data_width = 32;
|
parameter addr_width = 8;
|
parameter addr_width = 8;
|
|
parameter mem_size = 256;
|
input [(data_width-1):0] d;
|
input [(data_width-1):0] d;
|
input [(addr_width-1):0] adr;
|
input [(addr_width-1):0] adr;
|
input [(addr_width/4)-1:0] be;
|
input [(addr_width/4)-1:0] be;
|
input we;
|
input we;
|
output reg [(data_width-1):0] q;
|
output reg [(data_width-1):0] q;
|
input clk;
|
input clk;
|
`ifdef SYSTEMVERILOG
|
`ifdef SYSTEMVERILOG
|
logic [data_width/8-1:0][7:0] ram[0:1<<(addr_width-2)-1];// # words = 1 << address width
|
logic [data_width/8-1:0][7:0] ram[0:mem_size-1];// # words = 1 << address width
|
`else
|
`else
|
reg [data_width-1:0] ram [(1<<addr_width)-1:0];
|
reg [data_width-1:0] ram [mem_size-1:0];
|
`endif
|
`endif
|
parameter memory_init = 0;
|
parameter memory_init = 0;
|
parameter memory_file = "vl_ram.vmem";
|
parameter memory_file = "vl_ram.vmem";
|
generate if (memory_init) begin : init_mem
|
generate if (memory_init) begin : init_mem
|
initial
|
initial
|
begin
|
begin
|
$readmemh(memory_file, ram);
|
$readmemh(memory_file, ram);
|
end
|
end
|
end
|
end
|
endgenerate
|
endgenerate
|
`ifdef SYSTEMVERILOG
|
`ifdef SYSTEMVERILOG
|
// use a multi-dimensional packed array
|
// use a multi-dimensional packed array
|
//to model individual bytes within the word
|
//to model individual bytes within the word
|
always_ff@(posedge clk)
|
always_ff@(posedge clk)
|
begin
|
begin
|
if(we) begin // note: we should have a for statement to support any bus width
|
if(we) begin // note: we should have a for statement to support any bus width
|
if(be[3]) ram[adr[addr_width-2:0]][3] <= d[31:24];
|
if(be[3]) ram[adr[addr_width-2:0]][3] <= d[31:24];
|
if(be[2]) ram[adr[addr_width-2:0]][2] <= d[23:16];
|
if(be[2]) ram[adr[addr_width-2:0]][2] <= d[23:16];
|
if(be[1]) ram[adr[addr_width-2:0]][1] <= d[15:8];
|
if(be[1]) ram[adr[addr_width-2:0]][1] <= d[15:8];
|
if(be[0]) ram[adr[addr_width-2:0]][0] <= d[7:0];
|
if(be[0]) ram[adr[addr_width-2:0]][0] <= d[7:0];
|
end
|
end
|
q <= ram[adr];
|
q <= ram[adr];
|
end
|
end
|
`else
|
`else
|
genvar i;
|
genvar i;
|
generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
|
generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
|
always @ (posedge clk)
|
always @ (posedge clk)
|
if (we & be[i])
|
if (we & be[i])
|
ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
|
ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
|
end
|
end
|
endgenerate
|
endgenerate
|
always @ (posedge clk)
|
always @ (posedge clk)
|
q <= ram[adr];
|
q <= ram[adr];
|
`endif
|
`endif
|
endmodule
|
endmodule
|
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
|
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
|
parameter data_width = 32;
|
parameter data_width = 32;
|
parameter addr_width = 8;
|
parameter addr_width = 8;
|
input [(data_width-1):0] d_a;
|
input [(data_width-1):0] d_a;
|
input [(addr_width-1):0] adr_a;
|
input [(addr_width-1):0] adr_a;
|
input [(addr_width-1):0] adr_b;
|
input [(addr_width-1):0] adr_b;
|
input we_a;
|
input we_a;
|
output [(data_width-1):0] q_b;
|
output [(data_width-1):0] q_b;
|
input clk_a, clk_b;
|
input clk_a, clk_b;
|
reg [(addr_width-1):0] adr_b_reg;
|
reg [(addr_width-1):0] adr_b_reg;
|
reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
|
reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
|
parameter init = 0;
|
parameter init = 0;
|
parameter memory_file = "vl_ram.vmem";
|
parameter memory_file = "vl_ram.vmem";
|
generate if (init) begin : init_mem
|
generate if (init) begin : init_mem
|
initial
|
initial
|
begin
|
begin
|
$readmemh(memory_file, ram);
|
$readmemh(memory_file, ram);
|
end
|
end
|
end
|
end
|
endgenerate
|
endgenerate
|
always @ (posedge clk_a)
|
always @ (posedge clk_a)
|
if (we_a)
|
if (we_a)
|
ram[adr_a] <= d_a;
|
ram[adr_a] <= d_a;
|
always @ (posedge clk_b)
|
always @ (posedge clk_b)
|
adr_b_reg <= adr_b;
|
adr_b_reg <= adr_b;
|
assign q_b = ram[adr_b_reg];
|
assign q_b = ram[adr_b_reg];
|
endmodule
|
endmodule
|
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
|
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
|
parameter data_width = 32;
|
parameter data_width = 32;
|
parameter addr_width = 8;
|
parameter addr_width = 8;
|
input [(data_width-1):0] d_a;
|
input [(data_width-1):0] d_a;
|
input [(addr_width-1):0] adr_a;
|
input [(addr_width-1):0] adr_a;
|
input [(addr_width-1):0] adr_b;
|
input [(addr_width-1):0] adr_b;
|
input we_a;
|
input we_a;
|
output [(data_width-1):0] q_b;
|
output [(data_width-1):0] q_b;
|
output reg [(data_width-1):0] q_a;
|
output reg [(data_width-1):0] q_a;
|
input clk_a, clk_b;
|
input clk_a, clk_b;
|
reg [(data_width-1):0] q_b;
|
reg [(data_width-1):0] q_b;
|
reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
|
reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
|
parameter init = 0;
|
parameter init = 0;
|
parameter memory_file = "vl_ram.vmem";
|
parameter memory_file = "vl_ram.vmem";
|
generate if (init) begin : init_mem
|
generate if (init) begin : init_mem
|
initial
|
initial
|
begin
|
begin
|
$readmemh(memory_file, ram);
|
$readmemh(memory_file, ram);
|
end
|
end
|
end
|
end
|
endgenerate
|
endgenerate
|
always @ (posedge clk_a)
|
always @ (posedge clk_a)
|
begin
|
begin
|
q_a <= ram[adr_a];
|
q_a <= ram[adr_a];
|
if (we_a)
|
if (we_a)
|
ram[adr_a] <= d_a;
|
ram[adr_a] <= d_a;
|
end
|
end
|
always @ (posedge clk_b)
|
always @ (posedge clk_b)
|
q_b <= ram[adr_b];
|
q_b <= ram[adr_b];
|
endmodule
|
endmodule
|
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
|
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
|
parameter data_width = 32;
|
parameter data_width = 32;
|
parameter addr_width = 8;
|
parameter addr_width = 8;
|
input [(data_width-1):0] d_a;
|
input [(data_width-1):0] d_a;
|
input [(addr_width-1):0] adr_a;
|
input [(addr_width-1):0] adr_a;
|
input [(addr_width-1):0] adr_b;
|
input [(addr_width-1):0] adr_b;
|
input we_a;
|
input we_a;
|
output [(data_width-1):0] q_b;
|
output [(data_width-1):0] q_b;
|
input [(data_width-1):0] d_b;
|
input [(data_width-1):0] d_b;
|
output reg [(data_width-1):0] q_a;
|
output reg [(data_width-1):0] q_a;
|
input we_b;
|
input we_b;
|
input clk_a, clk_b;
|
input clk_a, clk_b;
|
reg [(data_width-1):0] q_b;
|
reg [(data_width-1):0] q_b;
|
reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
|
reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
|
parameter init = 0;
|
parameter init = 0;
|
parameter memory_file = "vl_ram.vmem";
|
parameter memory_file = "vl_ram.vmem";
|
generate if (init) begin : init_mem
|
generate if (init) begin : init_mem
|
initial
|
initial
|
begin
|
begin
|
$readmemh(memory_file, ram);
|
$readmemh(memory_file, ram);
|
end
|
end
|
end
|
end
|
endgenerate
|
endgenerate
|
always @ (posedge clk_a)
|
always @ (posedge clk_a)
|
begin
|
begin
|
q_a <= ram[adr_a];
|
q_a <= ram[adr_a];
|
if (we_a)
|
if (we_a)
|
ram[adr_a] <= d_a;
|
ram[adr_a] <= d_a;
|
end
|
end
|
always @ (posedge clk_b)
|
always @ (posedge clk_b)
|
begin
|
begin
|
q_b <= ram[adr_b];
|
q_b <= ram[adr_b];
|
if (we_b)
|
if (we_b)
|
ram[adr_b] <= d_b;
|
ram[adr_b] <= d_b;
|
end
|
end
|
endmodule
|
endmodule
|
// Content addresable memory, CAM
|
// Content addresable memory, CAM
|
// FIFO
|
// FIFO
|
module vl_fifo_1r1w_fill_level_sync (
|
module vl_fifo_1r1w_fill_level_sync (
|
d, wr, fifo_full,
|
d, wr, fifo_full,
|
q, rd, fifo_empty,
|
q, rd, fifo_empty,
|
fill_level,
|
fill_level,
|
clk, rst
|
clk, rst
|
);
|
);
|
parameter data_width = 18;
|
parameter data_width = 18;
|
parameter addr_width = 4;
|
parameter addr_width = 4;
|
// write side
|
// write side
|
input [data_width-1:0] d;
|
input [data_width-1:0] d;
|
input wr;
|
input wr;
|
output fifo_full;
|
output fifo_full;
|
// read side
|
// read side
|
output [data_width-1:0] q;
|
output [data_width-1:0] q;
|
input rd;
|
input rd;
|
output fifo_empty;
|
output fifo_empty;
|
// common
|
// common
|
output [addr_width:0] fill_level;
|
output [addr_width:0] fill_level;
|
input rst, clk;
|
input rst, clk;
|
wire [addr_width:1] wadr, radr;
|
wire [addr_width:1] wadr, radr;
|
vl_cnt_bin_ce
|
vl_cnt_bin_ce
|
# ( .length(addr_width))
|
# ( .length(addr_width))
|
fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
|
fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
|
vl_cnt_bin_ce
|
vl_cnt_bin_ce
|
# (.length(addr_width))
|
# (.length(addr_width))
|
fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
|
fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
|
vl_dpram_1r1w
|
vl_dpram_1r1w
|
# (.data_width(data_width), .addr_width(addr_width))
|
# (.data_width(data_width), .addr_width(addr_width))
|
dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
|
dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
|
vl_cnt_bin_ce_rew_q_zq_l1
|
vl_cnt_bin_ce_rew_q_zq_l1
|
# (.length(addr_width+1), .level1_value(1<<addr_width))
|
# (.length(addr_width+1), .level1_value(1<<addr_width))
|
fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
|
fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
|
endmodule
|
endmodule
|
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
|
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
|
// RAM is supposed to be larger than the two FIFOs
|
// RAM is supposed to be larger than the two FIFOs
|
// LFSR counters used adr pointers
|
// LFSR counters used adr pointers
|
module vl_fifo_2r2w_sync_simplex (
|
module vl_fifo_2r2w_sync_simplex (
|
// a side
|
// a side
|
a_d, a_wr, a_fifo_full,
|
a_d, a_wr, a_fifo_full,
|
a_q, a_rd, a_fifo_empty,
|
a_q, a_rd, a_fifo_empty,
|
a_fill_level,
|
a_fill_level,
|
// b side
|
// b side
|
b_d, b_wr, b_fifo_full,
|
b_d, b_wr, b_fifo_full,
|
b_q, b_rd, b_fifo_empty,
|
b_q, b_rd, b_fifo_empty,
|
b_fill_level,
|
b_fill_level,
|
// common
|
// common
|
clk, rst
|
clk, rst
|
);
|
);
|
parameter data_width = 8;
|
parameter data_width = 8;
|
parameter addr_width = 5;
|
parameter addr_width = 5;
|
parameter fifo_full_level = (1<<addr_width)-1;
|
parameter fifo_full_level = (1<<addr_width)-1;
|
// a side
|
// a side
|
input [data_width-1:0] a_d;
|
input [data_width-1:0] a_d;
|
input a_wr;
|
input a_wr;
|
output a_fifo_full;
|
output a_fifo_full;
|
output [data_width-1:0] a_q;
|
output [data_width-1:0] a_q;
|
input a_rd;
|
input a_rd;
|
output a_fifo_empty;
|
output a_fifo_empty;
|
output [addr_width-1:0] a_fill_level;
|
output [addr_width-1:0] a_fill_level;
|
// b side
|
// b side
|
input [data_width-1:0] b_d;
|
input [data_width-1:0] b_d;
|
input b_wr;
|
input b_wr;
|
output b_fifo_full;
|
output b_fifo_full;
|
output [data_width-1:0] b_q;
|
output [data_width-1:0] b_q;
|
input b_rd;
|
input b_rd;
|
output b_fifo_empty;
|
output b_fifo_empty;
|
output [addr_width-1:0] b_fill_level;
|
output [addr_width-1:0] b_fill_level;
|
input clk;
|
input clk;
|
input rst;
|
input rst;
|
// adr_gen
|
// adr_gen
|
wire [addr_width:1] a_wadr, a_radr;
|
wire [addr_width:1] a_wadr, a_radr;
|
wire [addr_width:1] b_wadr, b_radr;
|
wire [addr_width:1] b_wadr, b_radr;
|
// dpram
|
// dpram
|
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
|
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
|
vl_cnt_lfsr_ce
|
vl_cnt_lfsr_ce
|
# ( .length(addr_width))
|
# ( .length(addr_width))
|
fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
|
fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
|
vl_cnt_lfsr_ce
|
vl_cnt_lfsr_ce
|
# (.length(addr_width))
|
# (.length(addr_width))
|
fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
|
fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
|
vl_cnt_lfsr_ce
|
vl_cnt_lfsr_ce
|
# ( .length(addr_width))
|
# ( .length(addr_width))
|
fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
|
fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
|
vl_cnt_lfsr_ce
|
vl_cnt_lfsr_ce
|
# (.length(addr_width))
|
# (.length(addr_width))
|
fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
|
fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
|
// mux read or write adr to DPRAM
|
// mux read or write adr to DPRAM
|
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
|
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
|
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
|
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
|
vl_dpram_2r2w
|
vl_dpram_2r2w
|
# (.data_width(data_width), .addr_width(addr_width+1))
|
# (.data_width(data_width), .addr_width(addr_width+1))
|
dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
|
dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
|
.d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
|
.d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
|
vl_cnt_bin_ce_rew_zq_l1
|
vl_cnt_bin_ce_rew_zq_l1
|
# (.length(addr_width), .level1_value(fifo_full_level))
|
# (.length(addr_width), .level1_value(fifo_full_level))
|
a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
|
a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
|
vl_cnt_bin_ce_rew_zq_l1
|
vl_cnt_bin_ce_rew_zq_l1
|
# (.length(addr_width), .level1_value(fifo_full_level))
|
# (.length(addr_width), .level1_value(fifo_full_level))
|
b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
|
b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
|
endmodule
|
endmodule
|
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
|
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
|
parameter addr_width = 4;
|
parameter addr_width = 4;
|
parameter N = addr_width-1;
|
parameter N = addr_width-1;
|
parameter Q1 = 2'b00;
|
parameter Q1 = 2'b00;
|
parameter Q2 = 2'b01;
|
parameter Q2 = 2'b01;
|
parameter Q3 = 2'b11;
|
parameter Q3 = 2'b11;
|
parameter Q4 = 2'b10;
|
parameter Q4 = 2'b10;
|
parameter going_empty = 1'b0;
|
parameter going_empty = 1'b0;
|
parameter going_full = 1'b1;
|
parameter going_full = 1'b1;
|
input [N:0] wptr, rptr;
|
input [N:0] wptr, rptr;
|
output fifo_empty;
|
output fifo_empty;
|
output fifo_full;
|
output fifo_full;
|
input wclk, rclk, rst;
|
input wclk, rclk, rst;
|
wire direction;
|
wire direction;
|
reg direction_set, direction_clr;
|
reg direction_set, direction_clr;
|
wire async_empty, async_full;
|
wire async_empty, async_full;
|
wire fifo_full2;
|
wire fifo_full2;
|
wire fifo_empty2;
|
wire fifo_empty2;
|
// direction_set
|
// direction_set
|
always @ (wptr[N:N-1] or rptr[N:N-1])
|
always @ (wptr[N:N-1] or rptr[N:N-1])
|
case ({wptr[N:N-1],rptr[N:N-1]})
|
case ({wptr[N:N-1],rptr[N:N-1]})
|
{Q1,Q2} : direction_set <= 1'b1;
|
{Q1,Q2} : direction_set <= 1'b1;
|
{Q2,Q3} : direction_set <= 1'b1;
|
{Q2,Q3} : direction_set <= 1'b1;
|
{Q3,Q4} : direction_set <= 1'b1;
|
{Q3,Q4} : direction_set <= 1'b1;
|
{Q4,Q1} : direction_set <= 1'b1;
|
{Q4,Q1} : direction_set <= 1'b1;
|
default : direction_set <= 1'b0;
|
default : direction_set <= 1'b0;
|
endcase
|
endcase
|
// direction_clear
|
// direction_clear
|
always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
|
always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
|
if (rst)
|
if (rst)
|
direction_clr <= 1'b1;
|
direction_clr <= 1'b1;
|
else
|
else
|
case ({wptr[N:N-1],rptr[N:N-1]})
|
case ({wptr[N:N-1],rptr[N:N-1]})
|
{Q2,Q1} : direction_clr <= 1'b1;
|
{Q2,Q1} : direction_clr <= 1'b1;
|
{Q3,Q2} : direction_clr <= 1'b1;
|
{Q3,Q2} : direction_clr <= 1'b1;
|
{Q4,Q3} : direction_clr <= 1'b1;
|
{Q4,Q3} : direction_clr <= 1'b1;
|
{Q1,Q4} : direction_clr <= 1'b1;
|
{Q1,Q4} : direction_clr <= 1'b1;
|
default : direction_clr <= 1'b0;
|
default : direction_clr <= 1'b0;
|
endcase
|
endcase
|
vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
|
vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
|
assign async_empty = (wptr == rptr) && (direction==going_empty);
|
assign async_empty = (wptr == rptr) && (direction==going_empty);
|
assign async_full = (wptr == rptr) && (direction==going_full);
|
assign async_full = (wptr == rptr) && (direction==going_full);
|
vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
|
vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
|
vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
|
vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
|
/*
|
/*
|
always @ (posedge wclk or posedge rst or posedge async_full)
|
always @ (posedge wclk or posedge rst or posedge async_full)
|
if (rst)
|
if (rst)
|
{fifo_full, fifo_full2} <= 2'b00;
|
{fifo_full, fifo_full2} <= 2'b00;
|
else if (async_full)
|
else if (async_full)
|
{fifo_full, fifo_full2} <= 2'b11;
|
{fifo_full, fifo_full2} <= 2'b11;
|
else
|
else
|
{fifo_full, fifo_full2} <= {fifo_full2, async_full};
|
{fifo_full, fifo_full2} <= {fifo_full2, async_full};
|
*/
|
*/
|
/* always @ (posedge rclk or posedge async_empty)
|
/* always @ (posedge rclk or posedge async_empty)
|
if (async_empty)
|
if (async_empty)
|
{fifo_empty, fifo_empty2} <= 2'b11;
|
{fifo_empty, fifo_empty2} <= 2'b11;
|
else
|
else
|
{fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
|
{fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
|
vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
|
vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
|
vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty), .clk(rclk), .rst(async_empty));
|
vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty), .clk(rclk), .rst(async_empty));
|
endmodule // async_compb
|
endmodule // async_compb
|
module vl_fifo_1r1w_async (
|
module vl_fifo_1r1w_async (
|
d, wr, fifo_full, wr_clk, wr_rst,
|
d, wr, fifo_full, wr_clk, wr_rst,
|
q, rd, fifo_empty, rd_clk, rd_rst
|
q, rd, fifo_empty, rd_clk, rd_rst
|
);
|
);
|
parameter data_width = 18;
|
parameter data_width = 18;
|
parameter addr_width = 4;
|
parameter addr_width = 4;
|
// write side
|
// write side
|
input [data_width-1:0] d;
|
input [data_width-1:0] d;
|
input wr;
|
input wr;
|
output fifo_full;
|
output fifo_full;
|
input wr_clk;
|
input wr_clk;
|
input wr_rst;
|
input wr_rst;
|
// read side
|
// read side
|
output [data_width-1:0] q;
|
output [data_width-1:0] q;
|
input rd;
|
input rd;
|
output fifo_empty;
|
output fifo_empty;
|
input rd_clk;
|
input rd_clk;
|
input rd_rst;
|
input rd_rst;
|
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
|
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
|
vl_cnt_gray_ce_bin
|
vl_cnt_gray_ce_bin
|
# ( .length(addr_width))
|
# ( .length(addr_width))
|
fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
|
fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
|
vl_cnt_gray_ce_bin
|
vl_cnt_gray_ce_bin
|
# (.length(addr_width))
|
# (.length(addr_width))
|
fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
|
fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
|
vl_dpram_1r1w
|
vl_dpram_1r1w
|
# (.data_width(data_width), .addr_width(addr_width))
|
# (.data_width(data_width), .addr_width(addr_width))
|
dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
|
dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
|
vl_fifo_cmp_async
|
vl_fifo_cmp_async
|
# (.addr_width(addr_width))
|
# (.addr_width(addr_width))
|
cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
|
cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
|
endmodule
|
endmodule
|
module vl_fifo_2r2w_async (
|
module vl_fifo_2r2w_async (
|
// a side
|
// a side
|
a_d, a_wr, a_fifo_full,
|
a_d, a_wr, a_fifo_full,
|
a_q, a_rd, a_fifo_empty,
|
a_q, a_rd, a_fifo_empty,
|
a_clk, a_rst,
|
a_clk, a_rst,
|
// b side
|
// b side
|
b_d, b_wr, b_fifo_full,
|
b_d, b_wr, b_fifo_full,
|
b_q, b_rd, b_fifo_empty,
|
b_q, b_rd, b_fifo_empty,
|
b_clk, b_rst
|
b_clk, b_rst
|
);
|
);
|
parameter data_width = 18;
|
parameter data_width = 18;
|
parameter addr_width = 4;
|
parameter addr_width = 4;
|
// a side
|
// a side
|
input [data_width-1:0] a_d;
|
input [data_width-1:0] a_d;
|
input a_wr;
|
input a_wr;
|
output a_fifo_full;
|
output a_fifo_full;
|
output [data_width-1:0] a_q;
|
output [data_width-1:0] a_q;
|
input a_rd;
|
input a_rd;
|
output a_fifo_empty;
|
output a_fifo_empty;
|
input a_clk;
|
input a_clk;
|
input a_rst;
|
input a_rst;
|
// b side
|
// b side
|
input [data_width-1:0] b_d;
|
input [data_width-1:0] b_d;
|
input b_wr;
|
input b_wr;
|
output b_fifo_full;
|
output b_fifo_full;
|
output [data_width-1:0] b_q;
|
output [data_width-1:0] b_q;
|
input b_rd;
|
input b_rd;
|
output b_fifo_empty;
|
output b_fifo_empty;
|
input b_clk;
|
input b_clk;
|
input b_rst;
|
input b_rst;
|
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
|
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
|
vl_fifo_1r1w_async_a (
|
vl_fifo_1r1w_async_a (
|
.d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
|
.d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
|
.q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
|
.q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
|
);
|
);
|
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
|
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
|
vl_fifo_1r1w_async_b (
|
vl_fifo_1r1w_async_b (
|
.d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
|
.d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
|
.q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
|
.q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
|
);
|
);
|
endmodule
|
endmodule
|
module vl_fifo_2r2w_async_simplex (
|
module vl_fifo_2r2w_async_simplex (
|
// a side
|
// a side
|
a_d, a_wr, a_fifo_full,
|
a_d, a_wr, a_fifo_full,
|
a_q, a_rd, a_fifo_empty,
|
a_q, a_rd, a_fifo_empty,
|
a_clk, a_rst,
|
a_clk, a_rst,
|
// b side
|
// b side
|
b_d, b_wr, b_fifo_full,
|
b_d, b_wr, b_fifo_full,
|
b_q, b_rd, b_fifo_empty,
|
b_q, b_rd, b_fifo_empty,
|
b_clk, b_rst
|
b_clk, b_rst
|
);
|
);
|
parameter data_width = 18;
|
parameter data_width = 18;
|
parameter addr_width = 4;
|
parameter addr_width = 4;
|
// a side
|
// a side
|
input [data_width-1:0] a_d;
|
input [data_width-1:0] a_d;
|
input a_wr;
|
input a_wr;
|
output a_fifo_full;
|
output a_fifo_full;
|
output [data_width-1:0] a_q;
|
output [data_width-1:0] a_q;
|
input a_rd;
|
input a_rd;
|
output a_fifo_empty;
|
output a_fifo_empty;
|
input a_clk;
|
input a_clk;
|
input a_rst;
|
input a_rst;
|
// b side
|
// b side
|
input [data_width-1:0] b_d;
|
input [data_width-1:0] b_d;
|
input b_wr;
|
input b_wr;
|
output b_fifo_full;
|
output b_fifo_full;
|
output [data_width-1:0] b_q;
|
output [data_width-1:0] b_q;
|
input b_rd;
|
input b_rd;
|
output b_fifo_empty;
|
output b_fifo_empty;
|
input b_clk;
|
input b_clk;
|
input b_rst;
|
input b_rst;
|
// adr_gen
|
// adr_gen
|
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
|
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
|
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
|
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
|
// dpram
|
// dpram
|
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
|
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
|
vl_cnt_gray_ce_bin
|
vl_cnt_gray_ce_bin
|
# ( .length(addr_width))
|
# ( .length(addr_width))
|
fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
|
fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
|
vl_cnt_gray_ce_bin
|
vl_cnt_gray_ce_bin
|
# (.length(addr_width))
|
# (.length(addr_width))
|
fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
|
fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
|
vl_cnt_gray_ce_bin
|
vl_cnt_gray_ce_bin
|
# ( .length(addr_width))
|
# ( .length(addr_width))
|
fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
|
fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
|
vl_cnt_gray_ce_bin
|
vl_cnt_gray_ce_bin
|
# (.length(addr_width))
|
# (.length(addr_width))
|
fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
|
fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
|
// mux read or write adr to DPRAM
|
// mux read or write adr to DPRAM
|
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
|
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
|
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
|
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
|
vl_dpram_2r2w
|
vl_dpram_2r2w
|
# (.data_width(data_width), .addr_width(addr_width+1))
|
# (.data_width(data_width), .addr_width(addr_width+1))
|
dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
|
dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
|
.d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
|
.d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
|
vl_fifo_cmp_async
|
vl_fifo_cmp_async
|
# (.addr_width(addr_width))
|
# (.addr_width(addr_width))
|
cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
|
cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
|
vl_fifo_cmp_async
|
vl_fifo_cmp_async
|
# (.addr_width(addr_width))
|
# (.addr_width(addr_width))
|
cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
|
cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
|
endmodule
|
endmodule
|
module vl_reg_file (
|
module vl_reg_file (
|
a1, a2, a3, wd3, we3, rd1, rd2, clk
|
a1, a2, a3, wd3, we3, rd1, rd2, clk
|
);
|
);
|
parameter data_width = 32;
|
parameter data_width = 32;
|
parameter addr_width = 5;
|
parameter addr_width = 5;
|
input [addr_width-1:0] a1, a2, a3;
|
input [addr_width-1:0] a1, a2, a3;
|
input [data_width-1:0] wd3;
|
input [data_width-1:0] wd3;
|
input we3;
|
input we3;
|
output [data_width-1:0] rd1, rd2;
|
output [data_width-1:0] rd1, rd2;
|
input clk;
|
input clk;
|
vl_dpram_1r1w
|
vl_dpram_1r1w
|
# ( .data_width(data_width), .addr_width(addr_width))
|
# ( .data_width(data_width), .addr_width(addr_width))
|
ram1 (
|
ram1 (
|
.d_a(wd3),
|
.d_a(wd3),
|
.adr_a(a3),
|
.adr_a(a3),
|
.we_a(we3),
|
.we_a(we3),
|
.clk_a(clk),
|
.clk_a(clk),
|
.q_b(rd1),
|
.q_b(rd1),
|
.adr_b(a1),
|
.adr_b(a1),
|
.clk_b(clk) );
|
.clk_b(clk) );
|
vl_dpram_1r1w
|
vl_dpram_1r1w
|
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