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Line 1015... Line 1015...
//// You should have received a copy of the GNU Lesser General    ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
// LFSR counter
 
module vl_cnt_lfsr_ce (
 
 cke, zq, rst, clk);
 
   parameter length = 4;
 
   input cke;
 
   output reg zq;
 
   input rst;
 
   input clk;
 
   parameter clear_value = 0;
 
   parameter set_value = 1;
 
   parameter wrap_value = 0;
 
   parameter level1_value = 15;
 
   reg  [length:1] qi;
 
   reg lfsr_fb;
 
   wire [length:1] q_next;
 
   reg [32:1] polynom;
 
   integer i;
 
   always @ (qi)
 
   begin
 
        case (length)
 
         2: polynom = 32'b11;                               // 0x3
 
         3: polynom = 32'b110;                              // 0x6
 
         4: polynom = 32'b1100;                             // 0xC
 
         5: polynom = 32'b10100;                            // 0x14
 
         6: polynom = 32'b110000;                           // 0x30
 
         7: polynom = 32'b1100000;                          // 0x60
 
         8: polynom = 32'b10111000;                         // 0xb8
 
         9: polynom = 32'b100010000;                        // 0x110
 
        10: polynom = 32'b1001000000;                       // 0x240
 
        11: polynom = 32'b10100000000;                      // 0x500
 
        12: polynom = 32'b100000101001;                     // 0x829
 
        13: polynom = 32'b1000000001100;                    // 0x100C
 
        14: polynom = 32'b10000000010101;                   // 0x2015
 
        15: polynom = 32'b110000000000000;                  // 0x6000
 
        16: polynom = 32'b1101000000001000;                 // 0xD008
 
        17: polynom = 32'b10010000000000000;                // 0x12000
 
        18: polynom = 32'b100000010000000000;               // 0x20400
 
        19: polynom = 32'b1000000000000100011;              // 0x40023
 
        20: polynom = 32'b10010000000000000000;             // 0x90000
 
        21: polynom = 32'b101000000000000000000;            // 0x140000
 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
 
        default: polynom = 32'b0;
 
        endcase
 
        lfsr_fb = qi[length];
 
        for (i=length-1; i>=1; i=i-1) begin
 
            if (polynom[i])
 
                lfsr_fb = lfsr_fb  ~^ qi[i];
 
        end
 
    end
 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
 
   always @ (posedge clk or posedge rst)
 
     if (rst)
 
       qi <= {length{1'b0}};
 
     else
 
     if (cke)
 
       qi <= q_next;
 
   always @ (posedge clk or posedge rst)
 
     if (rst)
 
       zq <= 1'b1;
 
     else
 
     if (cke)
 
       zq <= q_next == {length{1'b0}};
 
endmodule
 
//////////////////////////////////////////////////////////////////////
 
////                                                              ////
 
////  Versatile counter                                           ////
 
////                                                              ////
 
////  Description                                                 ////
 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
 
////  counter                                                     ////
 
////                                                              ////
 
////  To Do:                                                      ////
 
////   - add LFSR with more taps                                  ////
 
////                                                              ////
 
////  Author(s):                                                  ////
 
////      - Michael Unneback, unneback@opencores.org              ////
 
////        ORSoC AB                                              ////
 
////                                                              ////
 
//////////////////////////////////////////////////////////////////////
 
////                                                              ////
 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
 
////                                                              ////
 
//// This source file may be used and distributed without         ////
 
//// restriction provided that this copyright statement is not    ////
 
//// removed from the file and that any derivative work contains  ////
 
//// the original copyright notice and the associated disclaimer. ////
 
////                                                              ////
 
//// This source file is free software; you can redistribute it   ////
 
//// and/or modify it under the terms of the GNU Lesser General   ////
 
//// Public License as published by the Free Software Foundation; ////
 
//// either version 2.1 of the License, or (at your option) any   ////
 
//// later version.                                               ////
 
////                                                              ////
 
//// This source is distributed in the hope that it will be       ////
 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
 
//// details.                                                     ////
 
////                                                              ////
 
//// You should have received a copy of the GNU Lesser General    ////
 
//// Public License along with this source; if not, download it   ////
 
//// from http://www.opencores.org/lgpl.shtml                     ////
 
////                                                              ////
 
//////////////////////////////////////////////////////////////////////
// GRAY counter
// GRAY counter
module vl_cnt_gray_ce_bin (
module vl_cnt_gray_ce_bin (
 cke, q, q_bin, rst, clk);
 cke, q, q_bin, rst, clk);
   parameter length = 4;
   parameter length = 4;
   input cke;
   input cke;
Line 1187... Line 1301...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
/// ROM
/// ROM
module vl_rom_init ( adr, q, clk);
module vl_rom_init ( adr, q, clk);
   parameter data_width = 32;
   parameter data_width = 32;
   parameter addr_width = 8;
   parameter addr_width = 8;
 
   parameter mem_size = 1<<addr_width;
   input [(addr_width-1):0]       adr;
   input [(addr_width-1):0]       adr;
   output reg [(data_width-1):0] q;
   output reg [(data_width-1):0] q;
   input                         clk;
   input                         clk;
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
   reg [data_width-1:0] rom [mem_size-1:0];
   parameter memory_file = "vl_rom.vmem";
   parameter memory_file = "vl_rom.vmem";
   initial
   initial
     begin
     begin
        $readmemh(memory_file, rom);
        $readmemh(memory_file, rom);
     end
     end
Line 1203... Line 1318...
endmodule
endmodule
// Single port RAM
// Single port RAM
module vl_ram ( d, adr, we, q, clk);
module vl_ram ( d, adr, we, q, clk);
   parameter data_width = 32;
   parameter data_width = 32;
   parameter addr_width = 8;
   parameter addr_width = 8;
 
   parameter mem_size = 1<<addr_width;
   input [(data_width-1):0]      d;
   input [(data_width-1):0]      d;
   input [(addr_width-1):0]       adr;
   input [(addr_width-1):0]       adr;
   input                         we;
   input                         we;
   output reg [(data_width-1):0] q;
   output reg [(data_width-1):0] q;
   input                         clk;
   input                         clk;
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
   reg [data_width-1:0] ram [mem_szie-1:0];
   parameter init = 0;
   parameter init = 0;
   parameter memory_file = "vl_ram.vmem";
   parameter memory_file = "vl_ram.vmem";
   generate if (init) begin : init_mem
   generate if (init) begin : init_mem
   initial
   initial
     begin
     begin
Line 1228... Line 1344...
   end
   end
endmodule
endmodule
module vl_ram_be ( d, adr, be, we, q, clk);
module vl_ram_be ( d, adr, be, we, q, clk);
   parameter data_width = 32;
   parameter data_width = 32;
   parameter addr_width = 6;
   parameter addr_width = 6;
   parameter mem_size = 256;
   parameter mem_size = 1<<addr_width;
   input [(data_width-1):0]      d;
   input [(data_width-1):0]      d;
   input [(addr_width-1):0]       adr;
   input [(addr_width-1):0]       adr;
   input [(data_width/8)-1:0]    be;
   input [(data_width/8)-1:0]    be;
   input                         we;
   input                         we;
   output reg [(data_width-1):0] q;
   output reg [(data_width-1):0] q;
Line 1277... Line 1393...
`endif
`endif
endmodule
endmodule
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
   parameter data_width = 32;
   parameter data_width = 32;
   parameter addr_width = 8;
   parameter addr_width = 8;
 
   parameter mem_size = 1<<addr_width;
   input [(data_width-1):0]      d_a;
   input [(data_width-1):0]      d_a;
   input [(addr_width-1):0]       adr_a;
   input [(addr_width-1):0]       adr_a;
   input [(addr_width-1):0]       adr_b;
   input [(addr_width-1):0]       adr_b;
   input                         we_a;
   input                         we_a;
   output [(data_width-1):0]      q_b;
   output [(data_width-1):0]      q_b;
   input                         clk_a, clk_b;
   input                         clk_a, clk_b;
   reg [(addr_width-1):0]         adr_b_reg;
   reg [(addr_width-1):0]         adr_b_reg;
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
   reg [data_width-1:0] ram [mem_szie-1:0] ;
   parameter init = 0;
   parameter init = 0;
   parameter memory_file = "vl_ram.vmem";
   parameter memory_file = "vl_ram.vmem";
   generate if (init) begin : init_mem
   generate if (init) begin : init_mem
   initial
   initial
     begin
     begin
Line 1304... Line 1421...
   assign q_b = ram[adr_b_reg];
   assign q_b = ram[adr_b_reg];
endmodule
endmodule
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
   parameter data_width = 32;
   parameter data_width = 32;
   parameter addr_width = 8;
   parameter addr_width = 8;
 
   parameter mem_size = 1<<addr_width;
   input [(data_width-1):0]      d_a;
   input [(data_width-1):0]      d_a;
   input [(addr_width-1):0]       adr_a;
   input [(addr_width-1):0]       adr_a;
   input [(addr_width-1):0]       adr_b;
   input [(addr_width-1):0]       adr_b;
   input                         we_a;
   input                         we_a;
   output [(data_width-1):0]      q_b;
   output [(data_width-1):0]      q_b;
   output reg [(data_width-1):0] q_a;
   output reg [(data_width-1):0] q_a;
   input                         clk_a, clk_b;
   input                         clk_a, clk_b;
   reg [(data_width-1):0]         q_b;
   reg [(data_width-1):0]         q_b;
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
   reg [data_width-1:0] ram [mem_szie-1:0] ;
   parameter init = 0;
   parameter init = 0;
   parameter memory_file = "vl_ram.vmem";
   parameter memory_file = "vl_ram.vmem";
   generate if (init) begin : init_mem
   generate if (init) begin : init_mem
   initial
   initial
     begin
     begin
Line 1334... Line 1452...
          q_b <= ram[adr_b];
          q_b <= ram[adr_b];
endmodule
endmodule
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
   parameter data_width = 32;
   parameter data_width = 32;
   parameter addr_width = 8;
   parameter addr_width = 8;
 
   parameter mem_size = 1<<addr_width;
   input [(data_width-1):0]      d_a;
   input [(data_width-1):0]      d_a;
   input [(addr_width-1):0]       adr_a;
   input [(addr_width-1):0]       adr_a;
   input [(addr_width-1):0]       adr_b;
   input [(addr_width-1):0]       adr_b;
   input                         we_a;
   input                         we_a;
   output [(data_width-1):0]      q_b;
   output [(data_width-1):0]      q_b;
   input [(data_width-1):0]       d_b;
   input [(data_width-1):0]       d_b;
   output reg [(data_width-1):0] q_a;
   output reg [(data_width-1):0] q_a;
   input                         we_b;
   input                         we_b;
   input                         clk_a, clk_b;
   input                         clk_a, clk_b;
   reg [(data_width-1):0]         q_b;
   reg [(data_width-1):0]         q_b;
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
   reg [data_width-1:0] ram [mem_size-1:0] ;
   parameter init = 0;
   parameter init = 0;
   parameter memory_file = "vl_ram.vmem";
   parameter memory_file = "vl_ram.vmem";
   generate if (init) begin : init_mem
   generate if (init) begin : init_mem
   initial
   initial
     begin
     begin
Line 1367... Line 1486...
        q_b <= ram[adr_b];
        q_b <= ram[adr_b];
        if (we_b)
        if (we_b)
          ram[adr_b] <= d_b;
          ram[adr_b] <= d_b;
     end
     end
endmodule
endmodule
 
module vl_dpram_be_2r2w ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
 
   parameter a_data_width = 32;
 
   parameter a_addr_width = 8;
 
   parameter b_data_width = 64;
 
   parameter b_addr_width = 7;
 
   //parameter mem_size = (a_addr_width>b_addr_width) ? (1<<a_addr_width) : (1<<b_addr_width);
 
   parameter mem_size = 1024;
 
   input [(a_data_width-1):0]      d_a;
 
   input [(a_addr_width-1):0]     adr_a;
 
   input [(b_addr_width-1):0]     adr_b;
 
   input [(a_data_width/4-1):0]    be_a;
 
   input                         we_a;
 
   output [(b_data_width-1):0]    q_b;
 
   input [(b_data_width-1):0]     d_b;
 
   output reg [(a_data_width-1):0] q_a;
 
   input [(b_data_width/4-1):0]    be_b;
 
   input                         we_b;
 
   input                         clk_a, clk_b;
 
   reg [(b_data_width-1):0]       q_b;
 
generate
 
if (a_data_width==32 & b_data_width==64) begin : inst32to64
 
    wire [63:0] temp;
 
    vl_dpram_2r2w
 
    # (.data_width(8), .addr_width(b_addr_width-3))
 
    ram0 (
 
        .d_a(d_a[7:0]),
 
        .q_a(tmp[7:0]),
 
        .adr_a(adr_a[a_addr_width-3-1:0]),
 
        .we_a(we_a & be_a[0] & !adr_a[0]),
 
        .clk_a(clk_a),
 
        .d_b(d_b[7:0]),
 
        .q_b(q_b[7:0]),
 
        .adr_b(adr_b[b_addr_width-3-1:0]),
 
        .we_b(we_b),
 
        .clk_b(clk_b) );
 
    vl_dpram_2r2w
 
    # (.data_width(8), .addr_width(b_addr_width-3))
 
    ram1 (
 
        .d_a(d_a[7:0]),
 
        .q_a(tmp[7:0]),
 
        .adr_a(adr_a[a_addr_width-3-1:0]),
 
        .we_a(we_a),
 
        .clk_a(clk_a),
 
        .d_b(d_b[7:0]),
 
        .q_b(q_b[7:0]),
 
        .adr_b(adr_b[b_addr_width-3-1:0]),
 
        .we_b(we_b),
 
        .clk_b(clk_b) );
 
    vl_dpram_2r2w
 
    # (.data_width(8), .addr_width(b_addr_width-3))
 
    ram2 (
 
        .d_a(d_a[15:8]),
 
        .q_a(tmp[7:0]),
 
        .adr_a(adr_a[a_addr_width-3-1:0]),
 
        .we_a(we_a),
 
        .clk_a(clk_a),
 
        .d_b(d_b[7:0]),
 
        .q_b(q_b[7:0]),
 
        .adr_b(adr_b[b_addr_width-3-1:0]),
 
        .we_b(we_b),
 
        .clk_b(clk_b) );
 
    vl_dpram_2r2w
 
    # (.data_width(8), .addr_width(b_addr_width-3))
 
    ram3 (
 
        .d_a(d_a[15:8]),
 
        .q_a(tmp[7:0]),
 
        .adr_a(adr_a[a_addr_width-3-1:0]),
 
        .we_a(we_a),
 
        .clk_a(clk_a),
 
        .d_b(d_b[7:0]),
 
        .q_b(q_b[7:0]),
 
        .adr_b(adr_b[b_addr_width-3-1:0]),
 
        .we_b(we_b),
 
        .clk_b(clk_b) );
 
    vl_dpram_2r2w
 
    # (.data_width(8), .addr_width(b_addr_width-3))
 
    ram4 (
 
        .d_a(d_a[23:16]),
 
        .q_a(tmp[7:0]),
 
        .adr_a(adr_a[a_addr_width-3-1:0]),
 
        .we_a(we_a),
 
        .clk_a(clk_a),
 
        .d_b(d_b[7:0]),
 
        .q_b(q_b[7:0]),
 
        .adr_b(adr_b[b_addr_width-3-1:0]),
 
        .we_b(we_b),
 
        .clk_b(clk_b) );
 
    vl_dpram_2r2w
 
    # (.data_width(8), .addr_width(b_addr_width-3))
 
    ram5 (
 
        .d_a(d_a[23:16]),
 
        .q_a(tmp[7:0]),
 
        .adr_a(adr_a[a_addr_width-3-1:0]),
 
        .we_a(we_a),
 
        .clk_a(clk_a),
 
        .d_b(d_b[7:0]),
 
        .q_b(q_b[7:0]),
 
        .adr_b(adr_b[b_addr_width-3-1:0]),
 
        .we_b(we_b),
 
        .clk_b(clk_b) );
 
    vl_dpram_2r2w
 
    # (.data_width(8), .addr_width(b_addr_width-3))
 
    ram6 (
 
        .d_a(d_a[31:24]),
 
        .q_a(tmp[7:0]),
 
        .adr_a(adr_a[a_addr_width-3-1:0]),
 
        .we_a(we_a),
 
        .clk_a(clk_a),
 
        .d_b(d_b[7:0]),
 
        .q_b(q_b[7:0]),
 
        .adr_b(adr_b[b_addr_width-3-1:0]),
 
        .we_b(we_b),
 
        .clk_b(clk_b) );
 
    vl_dpram_2r2w
 
    # (.data_width(8), .addr_width(b_addr_width-3))
 
    ram7 (
 
        .d_a(d_a[31:24]),
 
        .q_a(tmp[7:0]),
 
        .adr_a(adr_a[a_addr_width-3-1:0]),
 
        .we_a(we_a),
 
        .clk_a(clk_a),
 
        .d_b(d_b[7:0]),
 
        .q_b(q_b[7:0]),
 
        .adr_b(adr_b[b_addr_width-3-1:0]),
 
        .we_b(we_b),
 
        .clk_b(clk_b) );
 
/*
 
   reg [7:0] ram0 [mem_size/8-1:0];
 
   wire [7:0] wea, web;
 
   assign wea = we_a & be_a[0];
 
   assign web = we_b & be_b[0];
 
   always @ (posedge clk_a)
 
    if (wea)
 
        ram0[adr_a] <= d_a[7:0];
 
    always @ (posedge clk_a)
 
        q_a[7:0] <= ram0[adr_a];
 
   always @ (posedge clk_a)
 
    if (web)
 
        ram0[adr_b] <= d_b[7:0];
 
    always @ (posedge clk_b)
 
        q_b[7:0] <= ram0[adr_b];
 
*/
 
end
 
endgenerate
 
/*
 
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_rama
 
      always @ (posedge clk_a)
 
      if (we_a & be_a[i])
 
        ram[adr_a][(i+1)*8-1:i*8] <= d_a[(i+1)*8-1:i*8];
 
   end
 
   endgenerate
 
   always @ (posedge clk_a)
 
      q_a <= ram[adr_a];
 
   genvar i;
 
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ramb
 
      always @ (posedge clk_a)
 
      if (we_b & be_b[i])
 
        ram[adr_b][(i+1)*8-1:i*8] <= d_b[(i+1)*8-1:i*8];
 
   end
 
   endgenerate
 
   always @ (posedge clk_b)
 
      q_b <= ram[adr_b];
 
*/
 
/*
 
   always @ (posedge clk_a)
 
     begin
 
        q_a <= ram[adr_a];
 
        if (we_a)
 
             ram[adr_a] <= d_a;
 
     end
 
   always @ (posedge clk_b)
 
     begin
 
        q_b <= ram[adr_b];
 
        if (we_b)
 
          ram[adr_b] <= d_b;
 
     end
 
*/
 
endmodule
// Content addresable memory, CAM
// Content addresable memory, CAM
// FIFO
// FIFO
module vl_fifo_1r1w_fill_level_sync (
module vl_fifo_1r1w_fill_level_sync (
    d, wr, fifo_full,
    d, wr, fifo_full,
    q, rd, fifo_empty,
    q, rd, fifo_empty,
Line 1811... Line 2108...
        .clk(wbs_clk));
        .clk(wbs_clk));
always @ (posedge wbs_clk or posedge wbs_rst)
always @ (posedge wbs_clk or posedge wbs_rst)
if (wbs_rst)
if (wbs_rst)
        wbs <= wbs_adr;
        wbs <= wbs_adr;
else
else
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & a_fifo_empty)
                wbs <= wbs_data;
                wbs <= wbs_data;
        else if (wbs_eoc & wbs_ack_o)
        else if (wbs_eoc & wbs_ack_o)
                wbs <= wbs_adr;
                wbs <= wbs_adr;
// wbs FIFO
// wbs FIFO
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,((wbs_cti_i==3'b111) ? {2'b00,3'b000} : {wbs_bte_i,wbs_cti_i})} : {wbs_dat_i,wbs_sel_i};
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & a_fifo_empty :
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
              1'b0;
              1'b0;
assign a_rd = !a_fifo_empty;
assign a_rd = !a_fifo_empty;
always @ (posedge wbs_clk or posedge wbs_rst)
always @ (posedge wbs_clk or posedge wbs_rst)
if (wbs_rst)
if (wbs_rst)
Line 1923... Line 2220...
    .b_fifo_empty(b_fifo_empty),
    .b_fifo_empty(b_fifo_empty),
    .b_clk(wbm_clk),
    .b_clk(wbm_clk),
    .b_rst(wbm_rst)
    .b_rst(wbm_rst)
    );
    );
endmodule
endmodule
 
module vl_wb3avalon_bridge (
 
        // wishbone slave side
 
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
 
        // wishbone master side
 
        readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
 
input [31:0] wbs_dat_i;
 
input [31:2] wbs_adr_i;
 
input [3:0]  wbs_sel_i;
 
input [1:0]  wbs_bte_i;
 
input [2:0]  wbs_cti_i;
 
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
 
output [31:0] wbs_dat_o;
 
output wbs_ack_o;
 
input wbs_clk, wbs_rst;
 
input [31:0] readdata;
 
output [31:0] writedata;
 
output [31:2] address;
 
output [3:0]  be;
 
output write;
 
output read;
 
output beginbursttransfer;
 
output [3:0] burstcount;
 
input readdatavalid;
 
input waitrequest;
 
input clk;
 
input rst;
 
wire [1:0] wbm_bte_o;
 
wire [2:0] wbm_cti_o;
 
wire wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_ack_i;
 
reg last_cyc;
 
always @ (posedge clk or posedge rst)
 
if (rst)
 
    last_cyc <= 1'b0;
 
else
 
    last_cyc <= wbm_cyc_o;
 
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
 
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
 
                    (wbm_bte_o==2'b10) ? 4'd8 :
 
                    4'd16;
 
assign write = wbm_cyc_o & wbm_stb_o &  wbm_we_o;
 
assign read  = wbm_cyc_o & wbm_stb_o & !wbm_we_o;
 
assign wbm_ack_i = (readdatavalid & !waitrequest) | (write & !waitrequest);
 
vl_wb3wb3_bridge (
 
    // wishbone slave side
 
    .wbs_dat_i(wbs_dat_i),
 
    .wbs_adr_i(wbs_adr_i),
 
    .wbs_sel_i(wbs_sel_i),
 
    .wbs_bte_i(wbs_bte_i),
 
    .wbs_cti_i(wbs_cti_i),
 
    .wbs_we_i(wbs_we_i),
 
    .wbs_cyc_i(wbs_cyc_i),
 
    .wbs_stb_i(wbs_stb_i),
 
    .wbs_dat_o(wbs_dat_o),
 
    .wbs_ack_o(wbs_ack_o),
 
    .wbs_clk(wbs_clk),
 
    .wbs_rst(wbs_rst),
 
    // wishbone master side
 
    .wbm_dat_o(writedata),
 
    .wbm_adr_o(adress),
 
    .wbm_sel_o(be),
 
    .wbm_bte_o(wbm_bte_o),
 
    .wbm_cti_o(wbm_cti_o),
 
    .wbm_we_o(wbm_we_o),
 
    .wbm_cyc_o(wbm_cyc_o),
 
    .wbm_stb_o(wbm_stb_o),
 
    .wbm_dat_i(readdata),
 
    .wbm_ack_i(wbm_ack_i),
 
    .wbm_clk(clk),
 
    .wbm_rst(rst));
 
endmodule
module vl_wb3_arbiter_type1 (
module vl_wb3_arbiter_type1 (
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
    wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
    wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
    wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
    wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,

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