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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [wb.v] - Diff between revs 103 and 104

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endgenerate
endgenerate
 
 
endmodule
endmodule
`endif
`endif
 
 
 
`ifdef WB_B4_EOC
 
`define MODULE wb_b4_eoc
 
module `BASE`MODULE ( cyc_i, stb_i, stall_o, ack_o, busy, eoc, clk, rst);
 
`undef MODULE
 
input cyc_i, stb_i, ack_o;
 
output busy, eoc;
 
input clk, rst;
 
 
 
`define MODULE cnt_bin_ce_rew_zq_l1
 
`BASE`MODULE # ( .length(4), level1_value(1))
 
cnt0 (
 
    .cke(), .rew(), .zq(), .level1(), .rst(), clk);
 
`undef MODULE
 
 
 
endmodule
 
`endif
 
 
`ifdef WB3WB3_BRIDGE
`ifdef WB3WB3_BRIDGE
// async wb3 - wb3 bridge
// async wb3 - wb3 bridge
`timescale 1ns/1ns
`timescale 1ns/1ns
`define MODULE wb3wb3_bridge
`define MODULE wb3wb3_bridge
module `BASE`MODULE (
module `BASE`MODULE (
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`undef MODULE
`undef MODULE
 
 
endmodule
endmodule
`endif
`endif
 
 
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`ifdef WB_SDR_SDRAM
 
`define MODULE wb_sdr_sdram
 
module `BASE`MODULE (
 
`undef MODULE
 
    // wisbone i/f
 
    dat_i, adr_i, sel_i, we_i, cyc_i, stb_i, dat_o, ack_o, stall_o
 
    // SDR SDRAM
 
    ba, a, cmd, cke, cs_n, dqm, dq_i, dq_o, dq_oe,
 
    // system
 
    clk, rst);
 
 
 
    // external data bus size
 
    parameter dat_size = 16;
 
    // memory geometry parameters
 
    parameter ba_size  = `SDR_BA_SIZE;
 
    parameter row_size = `SDR_ROW_SIZE;
 
    parameter col_size = `SDR_COL_SIZE;
 
    parameter cl = 2;
 
    // memory timing parameters
 
    parameter tRFC = 9;
 
    parameter tRP  = 2;
 
    parameter tRCD = 2;
 
    parameter tMRD = 2;
 
 
 
    // LMR
 
    // [12:10] reserved
 
    // [9]     WB, write burst; 0 - programmed burst length, 1 - single location
 
    // [8:7]   OP Mode, 2'b00
 
    // [6:4]   CAS Latency; 3'b010 - 2, 3'b011 - 3
 
    // [3]     BT, Burst Type; 1'b0 - sequential, 1'b1 - interleaved
 
    // [2:0]   Burst length; 3'b000 - 1, 3'b001 - 2, 3'b010 - 4, 3'b011 - 8, 3'b111 - full page
 
    localparam init_wb = 1'b1;
 
    localparam init_cl = (cl==2) ? 3'b010 : 3'b011;
 
    localparam init_bt = 1'b0;
 
    localparam init_bl = 3'b000;
 
 
 
    input [dat_size:0] dat_i;
 
    input [ba_size+col_size+row_size-1:0] adr_i;
 
    input [dat_size/8-1:0] sel_i;
 
    input we_i, cyc_i, stb_i;
 
    output [dat_size-1:0] dat_o;
 
    output ack_o;
 
    output reg stall_o;
 
 
 
    output [ba_size-1:0]    ba;
 
    output reg [12:0]   a;
 
    output reg [2:0]    cmd; // {ras,cas,we}
 
    output cke, cs_n;
 
    output reg [dat_size/8-1:0]    dqm;
 
    output [dat_size-1:0]       dq_o;
 
    output reg          dq_oe;
 
    input  [dat_size-1:0]       dq_i;
 
 
 
    input clk, rst;
 
 
 
    wire [ba_size-1:0]   bank;
 
    wire [row_size-1:0] row;
 
    wire [col_size-1:0] col;
 
    wire [0:31]  shreg;
 
    wire                ref_cnt_zero;
 
    reg                 refresh_req;
 
 
 
    wire ack_rd, rd_ack_emptyflag;
 
    wire ack_wr;
 
 
 
    // to keep track of open rows per bank
 
    reg [row_size-1:0]   open_row[0:3];
 
    reg [0:3]            open_ba;
 
    reg                 current_bank_closed, current_row_open;
 
 
 
    parameter rfr_length = 10;
 
    parameter rfr_wrap_value = 1010;
 
 
 
    parameter [2:0] cmd_nop = 3'b111,
 
                    cmd_act = 3'b011,
 
                    cmd_rd  = 3'b101,
 
                    cmd_wr  = 3'b100,
 
                    cmd_pch = 3'b010,
 
                    cmd_rfr = 3'b001,
 
                    cmd_lmr = 3'b000;
 
 
 
// ctrl FSM
 
`define FSM_INIT 3'b000
 
`define FSM_IDLE 3'b001
 
`define FSM_RFR  3'b010
 
`define FSM_ADR  3'b011
 
`define FSM_PCH  3'b100
 
`define FSM_ACT  3'b101
 
`define FSM_RW   3'b111
 
 
 
    assign cke = 1'b1;
 
    assign cs_n = 1'b0;
 
 
 
    reg [2:0] state, next;
 
 
 
    function [12:0] a10_fix;
 
        input [col_size-1:0] a;
 
        integer i;
 
    begin
 
        for (i=0;i<13;i=i+1) begin
 
            if (i<10)
 
              if (i<col_size)
 
                a10_fix[i] = a[i];
 
              else
 
                a10_fix[i] = 1'b0;
 
            else if (i==10)
 
              a10_fix[i] = 1'b0;
 
            else
 
              if (i<col_size)
 
                a10_fix[i] = a[i-1];
 
              else
 
                a10_fix[i] = 1'b0;
 
        end
 
    end
 
    endfunction
 
 
 
    assign {bank,row,col} = adr_i;
 
 
 
    always @ (posedge clk or posedge rst)
 
    if (rst)
 
       state <= `FSM_INIT;
 
    else
 
       state <= next;
 
 
 
    always @*
 
    begin
 
        next = state;
 
        case (state)
 
        `FSM_INIT:
 
            if (shreg[3+tRP+tRFC+tRFC+tMRD]) next = `FSM_IDLE;
 
        `FSM_IDLE:
 
            if (refresh_req) next = `FSM_RFR;
 
            else if (cyc_i & stb_i & rd_ack_emptyflag) next = `FSM_ADR;
 
        `FSM_RFR:
 
            if (shreg[tRP+tRFC-2]) next = `FSM_IDLE; // take away two cycles because no cmd will be issued in idle and adr
 
        `FSM_ADR:
 
            if (current_bank_closed) next = `FSM_ACT;
 
            else if (current_row_open) next = `FSM_RW;
 
            else next = `FSM_PCH;
 
        `FSM_PCH:
 
            if (shreg[tRP]) next = `FSM_ACT;
 
        `FSM_ACT:
 
            if (shreg[tRCD]) next = `FSM_RW;
 
        `FSM_RW:
 
            if (!stb_i) next = `FSM_IDLE;
 
        endcase
 
    end
 
 
 
    // counter
 
`define MODULE cnt_shreg_ce_clear
 
    `VLBASE`MODULE # ( .length(32))
 
`undef MODULE
 
        cnt0 (
 
            .clear(state!=next),
 
            .q(shreg),
 
            .rst(rst),
 
            .clk(clk));
 
 
 
    // ba, a, cmd
 
    // outputs dependent on state vector
 
    always @ (*)
 
        begin
 
            {a,cmd} = {13'd0,cmd_nop};
 
            dqm = 2'b11;
 
            dq_oe = 1'b0;
 
            stall_o = 1'b1;
 
            case (state)
 
            `FSM_INIT:
 
                if (shreg[3]) begin
 
                    {a,cmd} = {13'b0010000000000, cmd_pch};
 
                end else if (shreg[3+tRP] | shreg[3+tRP+tRFC])
 
                    {a,cmd} = {13'd0, cmd_rfr};
 
                else if (shreg[3+tRP+tRFC+tRFC])
 
                    {a,cmd} = {3'b000,init_wb,2'b00,init_cl,init_bt,init_bl,cmd_lmr};
 
            `FSM_RFR:
 
                if (shreg[0])
 
                    {a,cmd} = {13'b0010000000000, cmd_pch};
 
                else if (shreg[tRP])
 
                    {a,cmd} = {13'd0, cmd_rfr};
 
            `FSM_PCH:
 
                if (shreg[0])
 
                    {a,cmd} = {13'd0,cmd_pch};
 
            `FSM_ACT:
 
                if (shreg[0])
 
                    {a[row_size-1:0],cmd} = {row,cmd_act};
 
            `FSM_RW:
 
                begin
 
                    if (we_i)
 
                        cmd = cmd_wr;
 
                    else
 
                        cmd = cmd_rd;
 
                    if (we_i)
 
                        dqm = ~sel_i;
 
                    else
 
                        dqm = 2'b00;
 
                    if (we_i)
 
                        dq_oe = 1'b1;
 
                    a = a10_fix(col);
 
                    stall_o = 1'b1;
 
                end
 
            endcase
 
        end
 
 
 
    assign ba = bank;
 
 
 
    // precharge individual bank A10=0
 
    // precharge all bank A10=1
 
    genvar i;
 
    generate
 
    for (i=0;i<2<<ba_size-1;i=i+1) begin
 
 
 
        always @ (posedge clk or posedge rst)
 
        if (rst)
 
            {open_ba[i],open_row[i]} <= {1'b0,{row_size{1'b0}}};
 
        else
 
            if (cmd==cmd_pch & (a[10] | bank==i))
 
                open_ba[i] <= 1'b0;
 
            else if (cmd==cmd_act & bank==i)
 
                {open_ba[i],open_row[i]} <= {1'b1,row};
 
 
 
    end
 
    endgenerate
 
 
 
    // bank and row open ?
 
    always @ (posedge clk or posedge rst)
 
    if (rst)
 
       {current_bank_closed, current_row_open} <= {1'b1, 1'b0};
 
    else
 
       {current_bank_closed, current_row_open} <= {!(open_ba[bank]), open_row[bank]==row};
 
 
 
    // refresh counter
 
`define MODULE cnt_lfsr_zq
 
    `VLBASE`MODULE # ( .length(rfr_length), .wrap_value (rfr_wrap_value)) ref_counter0( .zq(ref_cnt_zero), .rst(rst), .clk(clk));
 
`undef MODULE
 
 
 
    always @ (posedge clk or posedge rst)
 
    if (rst)
 
        refresh_req <= 1'b0;
 
    else
 
        if (ref_cnt_zero)
 
            refresh_req <= 1'b1;
 
        else if (state==`FSM_RFR)
 
            refresh_req <= 1'b0;
 
 
 
    assign dat_o = dq_i;
 
 
 
    assign ack_wr = (state==`FSM_RW & count0 & we_i);
 
`define MODULE delay_emptyflag
 
    `VLBASE`MODULE # ( .depth(cl+2)) delay0 ( .d(state==`FSM_RW & stb_i & !we_i), .q(ack_rd), .emptyflag(rd_ack_emptyflag), .clk(clk), .rst(rst));
 
`undef MODULE
 
    assign ack_o = ack_rd | ack_wr;
 
 
 
    assign dq_o = dat_i;
 
 
 
endmodule
 
`endif
 
 
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