| Line 1113... |
Line 1113... |
assign wb_ack_o = wb_ack;
|
assign wb_ack_o = wb_ack;
|
|
|
endmodule
|
endmodule
|
`endif
|
`endif
|
|
|
`ifdef WB_B3_DPRAM
|
`ifdef WB_DPRAM
|
`define MODULE wb_b3_dpram
|
`define MODULE wb_dpram
|
module `BASE`MODULE (
|
module `BASE`MODULE (
|
`undef MODULE
|
`undef MODULE
|
// wishbone slave side a
|
// wishbone slave side a
|
wbsa_dat_i, wbsa_adr_i, wbsa_sel_i, wbsa_cti_i, wbsa_bte_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
|
wbsa_dat_i, wbsa_adr_i, wbsa_sel_i, wbsa_cti_i, wbsa_bte_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o, wbsa_stall_o,
|
wbsa_clk, wbsa_rst,
|
wbsa_clk, wbsa_rst,
|
// wishbone slave side b
|
// wishbone slave side b
|
wbsb_dat_i, wbsb_adr_i, wbsb_sel_i, wbsb_cti_i, wbsb_bte_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
|
wbsb_dat_i, wbsb_adr_i, wbsb_sel_i, wbsb_cti_i, wbsb_bte_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o, wbsb_stall_o,
|
wbsb_clk, wbsb_rst);
|
wbsb_clk, wbsb_rst);
|
|
|
parameter data_width_a = 32;
|
parameter data_width_a = 32;
|
parameter data_width_b = data_width_a;
|
parameter data_width_b = data_width_a;
|
parameter addr_width_a = 8;
|
parameter addr_width_a = 8;
|
| Line 1140... |
Line 1140... |
input [2:0] wbsa_cti_i;
|
input [2:0] wbsa_cti_i;
|
input [1:0] wbsa_bte_i;
|
input [1:0] wbsa_bte_i;
|
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
|
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
|
output [data_width_a-1:0] wbsa_dat_o;
|
output [data_width_a-1:0] wbsa_dat_o;
|
output wbsa_ack_o;
|
output wbsa_ack_o;
|
|
output wbsa_stall_o;
|
input wbsa_clk, wbsa_rst;
|
input wbsa_clk, wbsa_rst;
|
|
|
input [data_width_b-1:0] wbsb_dat_i;
|
input [data_width_b-1:0] wbsb_dat_i;
|
input [addr_width_b-1:0] wbsb_adr_i;
|
input [addr_width_b-1:0] wbsb_adr_i;
|
input [data_width_b/8-1:0] wbsb_sel_i;
|
input [data_width_b/8-1:0] wbsb_sel_i;
|
input [2:0] wbsb_cti_i;
|
input [2:0] wbsb_cti_i;
|
input [1:0] wbsb_bte_i;
|
input [1:0] wbsb_bte_i;
|
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
|
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
|
output [data_width_b-1:0] wbsb_dat_o;
|
output [data_width_b-1:0] wbsb_dat_o;
|
output wbsb_ack_o;
|
output wbsb_ack_o;
|
|
output wbsb_stall_o;
|
input wbsb_clk, wbsb_rst;
|
input wbsb_clk, wbsb_rst;
|
|
|
wire [addr_width_a-1:0] adr_a;
|
wire [addr_width_a-1:0] adr_a;
|
wire [addr_width_b-1:0] adr_b;
|
wire [addr_width_b-1:0] adr_b;
|
wire we_a, we_b;
|
wire we_a, we_b;
|
